Arcam-CD62-cd-sm维修电路原理图.pdf

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1、CD62 DiVA CD62 Compact Disc Player (Text) Service Manual ARCAM Issue 1.0 RadioFans.CN 收音机爱 好者资料库 Contents List ! Contents list ! Circuit description ! Service guide ! Circuit diagrams ! Component overlays ! Circuit board parts list ! General assembly parts list RadioFans.CN 收音机爱 好者资料库 CD62 (text) Ci

2、rcuit Description Summary The main Motherboard/Display PCBs for the Diva CD players may be assembled as three different versions: ! DiVA CD62 (text) - With alternate components fitted and the 92DAC upgrade connections omitted (L933AY). ! DiVA CD72 (text) - With the standard set of components fitted

3、(L899AY). ! DiVA CD92 (text) - With analogue components and connectors omitted, for use as a host motherboard for the plug-in 92DAC (L934AY). All systems are based on a Sony kit, comprising CDM14BL- 5BD25 CD transport / loader / laser mechanism, micro-controller and fluorescent display. Power Suppli

4、es The CD62 may be fitted with any of the following transformers dependant on supply voltage required:- ! 230VAC only - part number L849TX ! 115VAC only - part number L850TX ! 100VAC only - part number L851TX Later models are fitted with L867TX which is a 230/115VAC transformer. The mains transforme

5、r has three secondary windings: 1. 13.7V 0V 13.7V to provide 12V(A) supplies (IC201 and IC205) for the audio output circuitry via regulators IC201 and IC205. 2. 9V-0V-32V to produce the digital, motor drive and fluorescent display grid supplies: +11V(U) Unregulated supply for relay drive and +5V(D)

6、supply +7V (IC200) Mechanism and motor driver supply +5V(D) (IC202) General digital logic supply +5V(A) (IC203) Supply to DAC -30V (IC204) Display grid voltage. 3. 0-5V to provide an AC supply for the display filament. Relay Mute Control This circuit drives a relay to un-mute the analogue output 5 s

7、econds after the unit is powered on, and quickly mutes the output when the unit is switched off. The circuit works effectively as an “AND” gate. If AC is present on the transformer secondary winding and the 5- second timer composed of R222 and C221 has reached the threshold voltage (Vbe of TR200 + V

8、be of TR201 - Vce of TR202, or 1.0V), the relay coil is connected to +11V (referenced to 0V_3 as required by the 9DACs internal circuitry) via TR204. When AC is removed, C231 discharges quickly through R225, the base voltage of TR204 rises and the relay coil voltage is removed, muting the output. TR

9、203 resets the timer by discharging C221 quickly at turn-off. Remote Control/PIC Micro Remote control data is received from the IREye on the display PCB and buffered by TR300 and TR301. The Programmable Interrupt Controller converts the RC-5 format data into the NEC format required by the Sony micro

10、. Motor Driver The status of the drawer is indicated to the micro by two micro switches INSW and OUTSW on SK205. The micro controls the drawer motor via driver IC303. Clock Buffering The clock and data signals LRCK, ADATA and BCLK from the mechanism connector SK300 are double buffered by IC300 befor

11、e being delivered to the DAC. Power-On/Reset The power-on reset signal XRST (or RESET) is generated by R409, C410 and IC404. When the power is turned on, C410 is initially uncharged and pin 11 of IC404 is at high voltage, and thus the output is low. After a short time, C410 is charged via R409; IC40

12、4 pin 11 is then low, and the output switches high (RESET is de-asserted). DAC & System Clock The DAC is a Burr Brown PCM1716E, the DAC is configured for hardware control. Digital audio is input on pins 1, 2 & 3 in standard Red Book Audio format, i.e. Word Clock, Bit Clock and Data. The system clock

13、 is based around 16.9344 MHZ crystal X400 and transistor TR402. This produces a stable clock with low jitter. IC404A & B buffer the clock as linear buffers. IC404C & D buffer the individual mech & DAC clock lines. Analogue Output Left channel: IC400A and IC400B are cascaded 69kHz 2nd order low-pass

14、Bessel filters. The output devices internal to both op-amps in IC400 are “pulled down” to the negative supply rail to force operation in class A (one output device is conducting at all times and crossover distortion is eliminated). C448 AC-couples the output, the muting relay shorts the output to gr

15、ound through 120 ohm series resistors, and 3N3 Polypropylene shunt capacitors are used to swamp cable capacitance, ensuring stability and making up the 5th pole of the filter. The right channel is the same as the left channel. IC401A & B are used as the buffer and filter. Microcontroller & Display B

16、oard The system microcontroller IC100 serves the following functions: ! Control of the mechanism & decoder on the CDM14 mechanism ! Control of mute, attenuation and de-emphasis for the DAC ! Direct drive of the fluorescent display ! Remote control decoding ! Keyboard scanning The keyboard scanning w

17、orks by connecting the keys to a resistor ladder on an ADC input to the micro. Pressing a key presents a unique voltage to this input, which the micro is pre-programmed to interpret accordingly. The remote control data contains a Customer Code that identifies this as an Arcam product. The diode netw

18、ork D100 to D106 configures the micro to accept this code. Remote Bus Carrier Filter & Demodulator Remote control commands can be delivered over wire to SK500 for multi-room applications. Incoming signals are attenuated and clipped by resistors and D500. L500 and C508 form a parallel resonant circui

19、t at approximately 37kHz. This demodulates the incoming signal and the output is passed to IC501A where it is chopped, low pass filtered and fed to IC501B to provide the RC5 output signal. Digital Output The decoder on the mechanism assembly generates an SPDIF format digital output signal. This is p

20、assed to buffer IC500A. IC500B through E are used in parallel to provide a transformer less 75-ohm source impedance to a single phono socket SK501. Optical digital output via IC502 is also tapped off the digital output signal via IC500F. Jumper Settings / Technical Specifications Jumper DescriptionJ

21、umperCD62T Settings CD72T Settings CD92T Settings Filter smoothing disable PL200 Not fitted Off On Filter smoothing disable PL201 Not fitted Off On IC201 Regulator bypass PL202 Not fitted Off On IC201 Regulator output enable PL203 On On Off IC205 Regulator bypass PL204 Not fitted Off On IC205 Regula

22、tor output enable PL205 On On Off System clock source select PL300 Pin1 & 2 Pins 1 & 2 Pins 2 & 3 Main board clock power enable PL400 On On Off Main board PCM1716E DAC enable PL401 On On Off Main board output relay enable PL402 On On Off CD62T / CD72T CD MechanismSony CDM14BL-5BD25 Laser pick-up3 be

23、am DAC conversion systemMulti-level Delta Sigma Effective resolution16 bits (24 bit capable DAC) Dynamic Range100dB Signal to Noise ratio (CCIR)104dB Harmonic distortion (0dBFS 1kHz)0.005% Harmonic distortion (0dBFS 10kHz)0.005% Frequency response (-0.7dB) 10Hz to 20kHz Output level (0dBFS)2.3VRMS O

24、utput impedance120 ohms Minimum recommended load5 k Coaxial digital output (75 ohm)Class 2 Power consumption (max)32VA Size W/D/H (mm)430 x290 x84 Weight, net4.6kg (CD92T 5.6kg) 12345678 A B C D 87654321 D C B A ISSUE DRAWING NO. 23425 DRAWING TITLE Drawn by: DATE Filename ECO No.DESCRIPTION OF CHAN

25、GE J:Change_ControlECO_AGENDA01_1127 CD62T RLEASEMotherboardl933ct_2.1.ddb - L933_2.1 prj A & R Cambridge Ltd. Pembroke Avenue Denny Industrial Centre Waterbeach Cambridge CB5 9PB CD62T - TOP LEVEL SCHEMATIC Circuit Diagram L933CT TGP19-Jul-2001 INITIALS Date Printed 67Sheetof Notes: FILA FILB L933C

26、2_1 L933C2_2.1.sch FILA FILB BCLK ADATA LRCKRC5 IP 17MHZ RESET DIGOP EMPHASIS L933C3_1 L933C3 2.1.sch DEEM LRCK ADATA BCLK RESET 17MHZ L933C4_1 L933C4 2.1.sch DIGOPRC5RP L933C5_1 L933C5 2.1.sch POWER SUPPLIES MECH INTERCONNECTSDAC AND OSCILLATOR RC5 INPUT AND DIG OUTPUTS 0V_1 0V_2 0V_SIG 0V_MOT 0V D

27、IG 0V_30V_9DAC FIX151 FIXING HOLE 3.2 FIX150 FIXING HOLE 3.5 FIX152 FIXING HOLE 3.5 FIX153 FIXING HOLE 3.5 FIX157 FIXING HOLE 3.2 FIX155 FIXING HOLE 3.5 FIX156 FIXING HOLE 3.5 FIX154 FIXING HOLE 3.5 (EARTH BY IEC SOCKET) C150 1N0 CDC151 1N0 CD C152 1N0 CD C153 1N0 CD C154 1N0 CD C155 1N0 CD C156 1N0

28、 CD 0V_DIG0V_DIG0V_DIG0V_DIG0V_DIG0V_DIG0V_DIG SP100 STARPOINT L933C7_1 L933C7 2.1.sch L933C1_1 L933C1 2.1.sch DISPLAY PCB DISPLAY AND MICROCONTROLLER 2.1 0V_DIG0V_9DAC LK601 0R0 MF LK600 0R0 MF Please refer to the CD72T (Master) schematic if changes are to be made to this schematic! USE EXCLUDE NF

29、WHEN CREATING BILL OF MATERIALS Production Release NF 01_1127TGP18 July 2001 12345678 A B C D 87654321 D C B A ISSUE DRAWING NO. 23425 DRAWING TITLE Drawn by: DATE Filename ECO No.DESCRIPTION OF CHANGE J:Change_ControlECO_AGENDA01_1127 CD62T RLEASEMotherboardl933ct_2.1.ddb - L933C2_2.1 sch A & R Cam

30、bridge Ltd. Pembroke Avenue Denny Industrial Centre Waterbeach Cambridge CB5 9PB CD62T - POWER SUPPLIES Circuit Diagram L933CT TGP19-Jul-2001 INITIALS Date Printed 27Sheetof Notes: L N E NEL SK200 IEC3 C200 3N3(X1Y2) C201 3N3(X1Y2) C203 220N(X2) NEUTRALLIVE NEUTRAL2 L200 6U8H L201 6U8H NEUTRAL2 FS20

31、1 T160MA FS200 T250MA115V 230V ONLY 115V ONLY EARTH LEAD 8M101 EL200 EARTH LEAD (IEC INLET TO CHASSIS) 1 2 3 4 5 6 SK202 MOLEXPWR6 (FOR AUX TOROID) SW200B A1010 SW200A A1010 LIVE2 C202 3N3(X1Y2) C204 100N CD C205 100N CD C206 100N CD C207 100N CD C208 100N CD R200 1R0 FU R201 1R0 FU BR201 DF01M + C2

32、11 1M0 35V + C212 1M0 35V 1 2 PL200 2WVERTJUMPER 1 2 PL201 2WVERTJUMPER JP200 JUMPER JP201 JUMPER Vin I ADJ A Vout O IC201 LM317T Vin I ADJ A Vout O IC205 LM337T R208 1K8 MF R209 1K8 MF R206 220R MF R207 220R MF + C216 100U EL + C217 100U EL D203 1N4148 D204 1N4148 1 2 PL203 2WVERTJUMPER 1 2 PL205 2

33、WVERTJUMPER 1 2 PL204 2WVERTJUMPER 1 2 PL202 2WVERTJUMPER JP202 JUMPER JP203 JUMPER JP205 JUMPER JP204 JUMPER +12V(A) -12V(A) 0V_1 BR200 DF01M+ C210 3M3 EL Vin I ADJ A Vout O IC200 LM1086-ADJ R203 330R MF R214 1K6 MF + C218 100U EL D201 1N4148 D200 1N4148 D202 1N4148 D207 1N4148 + C228 1M0 10V +7V 0

34、V_2 HS201 TO220HS30REG +11V(U) 1 2 3 4 SK201 MOLEXPWR4 (FOR AUX TOROID) Vin I ADJ A Vout O IC202 LM317T R218 270R MF R220 820R MF + C219 100U EL D208 1N4148 C209 100N CD D206 1N4148 + C220 100U EL +5V(D) 0V_2 +11V(U) Vin I ADJ A Vout O IC203 LM317T R219 270R MF R221 820R MF + C222 100U EL D212 1N414

35、8 D211 1N4148 +5V(A) 0V_1 Motor drive supply Analogue op-amp supplies DAC supply Digital +5V C215 100N PE + C223 1M0 25V + C224 1M0 25V R204 10R MF R205 10R MF + C229 1M0 10V R211 10R FU D213 1N4003 + C225 100U EL 100V Vin I ADJ A Vout O IC204 LM337T R216 1K0 MF R215 22K MF + C227 100U EL 100V D205

36、1N4148 -30VF R217 33K MF FILA FILB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SK203 FFC23V +12V(A) 0V_9DAC -12V(A) +5V(A) +5V(D) +11V(U) Power connector for 9DAC PCB + C226 100U EL 100V C213 100N PE C214 100N PE D209 1N4148 D210 1N4148 0V_3 R224 10K MF + C230 100U EL + C231 10U EL A

37、C1 AC2 AC1 Relay control for AC detect HS202 TO220HS30REG Filiament supply 115V 230V AC 3 TX_19 TX_20 TX_16 TX 18 BLU BLU BRNBRN R2101R0 FU R212 1R0 FU R228 100R MF R227 100R MF RLYPWR D214 5V1 400MW NF NF R202 1M5 VR25 R223 10K MF R213 10R FU D215 1N4148 + C221 100U EL TR204 BC557B R229 1K5 MF R226

38、 10K MF AC2 R230 10K MF 0V_3 0V_3 R225 2K2 MF R222 470K MF TR200 BC549B TR201 BC549B TR202 BC549BTR203 BC549B NF NF NFNF NF NF NF NF NF NB: CABLE ASSEMBLY L920CA GOES BETWEEN BRN BRN AND BLU BLU FROM MAINS SWITCH TO BACK OF PCB L920CA CA1 L920CA HS HS200 TO220HS08REG 2.1TGP18 July 2001 20 11 1 6 230

39、V 115V 9 19 15 18 16 17 13 4 5 10 2 7 TX200 L849TX Production Release01_1127 12345678 A B C D 87654321 D C B A ISSUE DRAWING NO. 23425 DRAWING TITLE Drawn by: DATE Filename ECO No.DESCRIPTION OF CHANGE J:Change_ControlECO_AGENDA01_1127 CD62T RLEASEMotherboardl933ct_2.1.ddb - L933C3_2.1.sch A & R Cam

40、bridge Ltd. Pembroke Avenue Denny Industrial Centre Waterbeach Cambridge CB5 9PB CD62T - MECH CONNECTS, MOTOR DRIVE AND IR MICRO Circuit Diagram L933CT TGP19-Jul-2001 INITIALS Date Printed 37Sheetof Notes: 1 2 3 PL300 3WVERTJUMPER FILA FILB Flexfoil connector to Display PCB 1 2 3 4 5 6 7 8 9 10 11 1

41、2 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SK302 FFC32V Data connector to DAC PCB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SK301 FFC32V HDCD DEEM RA0 RB6 RB5 RB4 RB0 XRST AMUTE BCLK DATA CLK SUBQ SENS XLT LDON AMUTE SQCK SCOR 1 2 3 4 5

42、 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SK300 FFC23V XRST LPH RA2 1 RA3 2 RTCC 3 MCLR 4 VSS 5 RB0 6 RB1 7 RB2 8 RB3 9 RB4 10 RB5 11 RB6 12 RB7 13 VDD 14 OSC2 15 OSC1 16 RA0 17 RA1 18 IC302 PIC16C54XT RA0 AMUTE RB0 RB4 RB5 RB6 RMIN XRST +5V(D) R311 100K MF +5V(D) DEEM IREYE C304 100P CD D3

43、00 1N4148 +5V(D) BCLK ADATA LRCK GND 1 O/P In 2 3 Bias 4 LoadIn 5 LoadOut 6 Vcc 7 Vcc 8 9 O/P Out 10 IC303 LB1641 1 2 3 4 5 SK303 8K2005 C307 10N CD D301 4V7 400MW LOADOUT LOADIN GND INSW OUTSW +7V R312 6K8 MF C303 100N CD + C306 100U EL X300 CST4.00 C302 100N CD + C305 100U EL C300 100N CD +5V(D) F

44、lex connector from CDM14BL-5BD25 mech R300 330R MF R304 330R MF R306 330R MF R309 10K MF R308 10K MF R310 10K MF R307 10K MF RC5 IP +5V(D) 0V_DIG +7V ADATA LRCK 0V_DIG +5V(D) 0V_9DAC R301 330R MF R302 330R MF R305 330R MF C301 100N CD 0V_DIG LRCK ADATA BCLK 17MHZ TR300 BC549B TR301 BC549B 0V_DIG 0V_

45、DIG 0V_DIG RESET -30VF +5V(D) 0V_DIG SCOR IREYE RMIN HDCD LDOUT LDIN SENS XLT AMUTE CLK LDON DATA SQCK SUBQ LOADSW XRST LPH DEEM DIGOP 0V_MOT 0V_MOT LOADSW LDIN LDOUT EMPHASIS Motor Drive R303 6K8 MF +5V(D) C308 100N CD (From 9 DAC PCB) JP300 JUMPER (Master clock select jumper) (From crystal oscilla

46、tor) R313 100K MF R314 10K MF 0V_DIG R315 10K MF 0V_DIG 12 IC300A 74HCU04 34 IC300B 74HCU04 56 IC300C 74HCU04 89 IC300D 74HCU04 1011 IC300E 74HCU04 1213 IC300F 74HCU04 14 7 IC300G 74HCU04 NF NF NF NF 2.1TGP18 July 2001Production Release01_1127 12345678 A B C D 87654321 D C B A ISSUE DRAWING NO. 2342

47、5 DRAWING TITLE Drawn by: DATE Filename ECO No.DESCRIPTION OF CHANGE J:Change_ControlECO_AGENDA01_1127 CD62T RLEASEMotherboardl933ct_2.1.ddb - L933C4_2.1 sch A & R Cambridge Ltd. Pembroke Avenue Denny Industrial Centre Waterbeach Cambridge CB5 9PB CD62T - DAC, OSCILLATOR AND ANALOGUE OUTPUTS Circuit

48、 Diagram L933CT TGP19-Jul-2001 INITIALS Date Printed 47Sheetof Notes: X400 16.9344MHZ C441 33P CD R426 33K MF R427 33K MF C438 100P CD C439 100P CD R430 1K0 MF TR402 BC547B C412 10N CD C440 1N0 CD 34 IC404B 74HCU04 12 IC404A 74HCU0456 IC404C 74HCU04 1011 IC404E 74HCU04 89 IC404D 74HCU04 14 7 IC404G

49、74HCU04 R429 4M7 MF R428 330R MF L403 33UH AX C437 10N CD 0V_DIG DEEM +5V(DAC) 0V_SIG 0V_SIG 0V_SIG +5V(DAC) 0V_DIG +5V(DAC) 0V DIG 0V_SIG 0V_SIG +5V(DAC) +5V(DAC) R409 10K MF D400 1N4148 0V_DIG +5V(D) R413 4K7 MF R415 2K7 MF R410 6K8 MF C416 560P PP C418 220P PP R416 2K7 MF R403 1K8 MF C422 1N3 PP C420 220P PP R419 3K9 MF 3 2 1 IC400A NJM2114 5 6 7 IC400B NJM2114 0V_SIG 84 IC400C NJM2114 3 2 1 IC402A TL072 84 IC402C TL072 C424 470N PE 0V_SIG R42