Denon-S101-hts-sm维修电路图 手册.pdf
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1、SERVICE MANUAL DVD HOME THEATER SYSTEM MODEL S-101 TOKYO, JAPAN Denon Brand Company, D 1IN/LOW; 2IN) 31 R-Y1 INPUT 30 B-Y1 INPUT 29 Y1 INPUT 28 I2C GND 27 R-Y2 INPUT 26 B-Y2 INPUT 25 Y2 INPUT 24 23 22 21 20 19 18 17 16 15 SW GND ADRS SW R Y/R OUTPUT B Y/B OUTPUT Y/G OUTPUT SW Vcc (9V) SYNC Vcc (9V)
2、CP/HP NPUT Dig GND SCP OUTPUT DAC2 DAC1 fsc Y DL Y DL SW SW PEDESTAL CLAMP 1H DL CONTROL SECAM CONTROL CbCr / UV SW sc TRAP OFFSET SW LPF / sc TRAP BPFH AFCH C / D 32fH VCO V C / D ACC TOF SCP SW APC P / N ID SYSTEM CW MATRIX T NT DEMO CHROMA BLK NOSE DET YUV RGB MATRIX CP / HP N SW V SEP SYNC SEP S
3、UB COLOR VCXO SUB CONTRAST Y OFFSET SW DAC TEST Ys 2C BUS CONTROL PEDESTAL CLAMP PEDESTAL CLAMP HI 20h/LOW 24h RadioFans.CN 31 S-101 TAS5121 (IC201, 301, 401: 1U-3683) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 GND PWM_BP GND RESET DREG_RTN GVD
4、D M3 DREG DGND M1 M2 DVDD SD DGND OTW GND PWM_AP GND GVDD_B GVDD_B GND BST_B PVDD_B PVDD_B OUT_B OUT_B GND GND OUT_A OUT_A PVDD_A PVDD_A BST_A GND GVDD_A GVDD_A Terminal Functions TERMINAL FUNCTION(1)DESCRIPTION NAMEDKD FUNCTION(1)DESCRIPTION BST_A22PHigh-side bootstrap supply (BST), external resist
5、or and capacitor to OUT_A required BST_B33PHigh-side bootstrap supply (BST), external resistor and capacitor to OUT_B required DGND9, 14PI/O reference ground DREG8PDigital supply voltage regulator decoupling pin, 1-F capacitor connected to DREG_RTN DREG_RTN5PDecoupling return pin DVDD12PI/O referenc
6、e supply input: 100 to DREG, decoupled to GND, 0.1-F capacitor connected to GND GND1, 3, 16, 18, 21, 27, 28, 34 PPower ground, connected to system GND GVDD6PLocal GVDD decoupling pin GVDD_A19, 20PGate drive input voltage GVDD_B35, 36PGate drive input voltage M110IProtection mode selection pin, conne
7、ct to GND M211IProtection mode selection pin, connect to DREG M37IOutput mode selection pin; connect to GND OTW15OOvertemperature warning output, open drain with internal pullup resistor, active-low when temper- ature exceeds 115C OUT_A25, 26OOutput, half-bridge A OUT_B29, 30OOutput, half-bridge B P
8、VDD_A23, 24PPower supply input for half-bridge A PVDD_B31, 32PPower supply input for half-bridge B PWM_AP17IPWM input signal, half-bridge A PWM_BP2IPWM input signal, half-bridge B RESET4IReset signal, active-low SD13OShutdown signal for half-bridges A and B (open drain with internal pullup resistor)
9、, active-low (1)I = input, O = Output, P = Power RadioFans.CN 32 S-101 BH7868FS (IC301, 302: 1U-3695) LC72720NM (IC506: 1U-3694) Vcc1 S1 S2 CIN MUTE1 CVIN SEL (CV/MIX) YIN BIAS SEL (BIAS/CLAMP) Py/G IN GND Pb/B IN MUTE2 Pr/R IN Vcc2 COUT S-DCOUT CVOUT CVOUT GND YOUT YOUT SAG GND Py/G OUT Py/G OUT SA
10、G GND Pb/B OUT Pb/B OUT SAG GND Pr/R OUT Pr/R OUT SAG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1617 18 19 20 21 22 23 24 25 26 27 28 29 30 31 3275 75 6dBBias Bias Bias Bias 6dBClamp 6dBClamp Clamp MUTE1 MUTE2 H L 6MHz LFP S-DCOUT LPF 6MHz LFP 75 6MHz LFP 75 L H 12MHz LFP 6dB 75 12MHz LFP 6dB Bias75 12MHz
11、 LFP 6dB 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 Vref MPXIN Vdda Vssa FLOUT CIN T1 T2 T3 (RDCL) T4 (RDDA) T5 (RSFT) XOUT SYR CE DI CL DO RDS-ID SYNC T7 (CORREC/ARI-ID/BEO) T6 (ERROR/57K/BE1) Vssd Vddd XIN REFERENCE VOLTAGE ANTIALIASING FILTER 57kHz BPF (SCF) SMOOTHING FILTER P
12、LL (57kHz) CLOCK RECOVERY (1167.5Hz) RAM (24 BLOCK DATA) ERROR CORRECTION (SOFT DECISION) DATA DECODER SYNC/EC CONTROLLER CCB TEST VREF VREF MEMORY CONTROL OSC/DIVIDER SYNC DETECT-1 SYNC DETECT-2 CLK(4.332MHz) FLOUTCIN Vdda Vssa MPXIN DO CL DI CE T1 T2 T3 T7 XINXOUT Vddd Vssd RDS-ID SYNC SYR RadioFa
13、ns.CN 33 S-101 NJM2596 (IC509: 1U-3695) SN74LV573APW (IC903, 904: 1U-3694) PCM1803 (IC803, 804: 1U-3683) 112 1324 1 2 3 4 5 6 7 8 10 9 20 19 18 17 16 15 14 13 12 11 OE D0 D1 D2 D3 D4 D5 D6 D7 GND Vcc Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 LE D Q L D Q L D Q L D Q L D Q L D Q L D Q L D Q L D0D1D2D3D4D5D6D7 L E OE 1
14、 23456789 11 1213141516171819 Q0Q1Q2Q3Q4Q5Q6Q7 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VINL VINR VREF1 VREF2 VCC AGND PDWN BYPAS TEST LRCK MODE1 MODE0 FMT1 FMT0 OSR SCKI VDD DGND DOUT BCK BLOCK DIAGRAM BCK VINL Reference VREF1 VREF2 VINR DeltaSigma Modulator DeltaSigma Modulator 1/64 , 1/
15、128 Decimation Filter With HighPass Filter Power Supply AGNDVCCVDDDGND Clock and Timing Control Serial Interface Mode/ Format Control LRCK DOUT FMT0 FMT1 MODE0 MODE1 BYPAS OSR PDWN SCKI TEST RadioFans.CN 34 S-101 QT240 (IC306: 1U-3681) SN74LV244APW (IC708, 719: 1U-3694)BU2090F (IC303: 1U-3681) SN74H
16、CT244APW (IC205: 1U-3694)(IC304, 504: 1U-3695) NJM2595 (IC507, 508: 1U-3695) SN74LV157APW (IC704: 1U-3694)SN74LVC139APWR (IC902: 1U-3694) SNS1 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 SNS1K OUT1 OUT2 VSS OUT3 SS/SYNC n.c. OSC OUT4 /RES VDD SNS4 SNS4K SNS3K SNS3SNS2K QT240 20-SSOP SNS2 10 19 20 n.c.
17、n.c. Sense pin (to Cs3, electrode); OPT1SNS3K20 Sense pin (to Rs3 + Cs3)SNS319 Sense pin (to Cs4, electrode); OPT2SNS4K18 Sense pin (to Rs4 + Cs4)SNS417 Ground or no connectVSS16 Oscillator bias inOSC15 Power: +4 0 to +5V locally regulatedVDD14 Reset pin, active low. Can usually tie to Vdd./RES13 Ou
18、tput, key 4OUT412 Unbonded internallyn.c.11 Unbonded internallyn.c.10 Sync in and/or spread spectrum driveSYNC/SS9 GroundVSS8 Output, key 3OUT37 Output, key 2OUT26 Output, key 1OUT15 Sense pin (to Cs1, electrode); speed optionSNS1K4 Sense pin (to Rs1 + Cs1)SNS13 Sense pin (to Cs2, electrode)SNS2K2 S
19、ense pin (to Rs2 + Cs2)SNS21 DescriptionNamePin TABLE 1-1 PIN LISTING - QT240-ISS 1 2 3 4 5 6 7 8 20 19 18 16 15 14 13 I3 VCC OE2 O2 I5 O0 I4 O1 I6 OE I0 O4 I1 O5 I2 O6 912 O7O3 1011 GNDI7 17 1 2 3 4 5 6 7 8 18 17 16 15 14 13 12 11Q3 VDD OE Q7 Q8 Q11 Q10 Q9 Q6 VSS DATA CLOCK LCK Q0 Q1 Q2 910Q4Q5 CON
20、TROL CIRCUIT 12-bitSHIFTREGISTER 12-bitSTRAGEREGISTER O U T P U TB U FFE R(O P E ND R AN ) 1 8 916 1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Vcc ST 4A 4B 4Y 3A 3B 3Y SELECT 5 SEL 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1G 1A 1B 1Y0 1Y1 1Y2 1Y3 GND VCC 2G 2A 2B 2Y0 2Y1 2Y2 2Y3 FUNCT
21、ION TABLE (each decoder/demultiplexer) INPUTS OUTPUTS G SELECT OUTPUTS G BAY3Y2Y1Y0 LLLHHHL LLHHHLH LHLHLHH LHHLHHH HXXHHHH RadioFans.CN 35 S-101 BU4053BCF (IC510: 1U-3695)BU4052BCF (IC518: 1U-3695) TC74VHC74FT (IC703: 1U-3694)NJM2274R (IC502: 1U-3695) BR93L86RFVM-WTR (IC201: 1U-3694) Y1 Y0 Z1 Z Z0
22、INH VEE Vss VDD Y X X1 X0 A B C 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 C Y X X1 X0 A B Y0 Z1 Z Z0 INH VEE Y1 Y0 Y2 COMMON Y Y3 Y1 INH VEE Vss VDD X2 X1 COMMON X X0 X3 A B 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 B X2 X1 XOUT /IN X0 X3 A Y2 YOUT /IN Y3 Y1 INH VEE Y0 1 2 3 45 7 8 6 TOP VIEW 1Yin Cin 7 C
23、 Mute CTL 2 GND Disc. Vref 7 Power Save CTL 2 Vcc Clamp 8Bias + + V4 3 V 750 ohm CS SK DI 1 2 3 4 8 7 6 5DO Vcc N.C. GND. 16bits 16bits 10bits 10bits CS SK DI DO INSTRUCTION DECODE CONTROL AND CLOCK GENERATION INSTRUCTION REGISTER DUMMY BIT ADDRESS BUFFER DATA REGISTER DETECT SUPPLY VOLTAGE WRITE DI
24、SABLE HIGE VOLTAGE GENERATOR R / W AMPS 16,384-bits EEPROM ADDRESS DECODE N.C. RadioFans.CN 36 S-101 BD9781HFP (IC810: 1U-3695) BD9002HFP (IC811: 1U-3695) BD4828G (IC203: 1U-3694)LM3671 (IC912: 1U-3694) 1234567 BD9781HVFP 5 3 4 1 2 7 6 535V VIN INV Vref OSC FB RT CURRENT LIMIT ERROR AMPPWM SW EN/SYN
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