Denon-DRAF109-rec-sm维修电路图 手册.pdf
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1、D D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output (2)All pullups are 200-mA weak pullups and all pulldowns are 200-mA weak pulldowns. The pullups and pulldowns are included to ensure proper input logic levels if the terminals are left unconnected (pullups = logic-1 input; pulld
2、owns = logic-0 input). Devices that drive inputs with pullups must be able to sink 200 mA, while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be able to source 200 mA, while maintaining a logic-1 drive level. RadioFans.CN 60 TERMINAL 5-V TYPE(1)TERMINATION(2)DESCR
3、IPTION TOLERANT NAMENO. PWM_P_345DOPWM 3 output (differential +) PWM_P_447DOPWM 4 output (differential +) PWM_P_556DOPWM 5 output (differential +) PWM_P_658DOPWM 6 output (differential +) PWM_P_750DOPWM 7 (lineout L) output (differential +) PWM_P_852DOPWM 8 (lineout R) output (differential +) RESERV
4、ED21, 22,Connect to digital ground 23, 64 RESET11DI5 VPullupSystem reset input, active-low. A system reset is generated by applying a logic low to this terminal. RESET is an asynchronous control signal that restores the TAS5508 to its default conditions, sets the valid output low, and places the PWM
5、 in the hard mute (M) state. Master volume is immediately set to full attenuation. On the release of RESET, if PDN is high, the system performs a 4- to 5-ms device initialization and sets the volume at mute. SCL25DI5 V I2C serial-control clock input/output SCLK27DI5 VSerial-audio data clock (shift c
6、lock) input SDA24DIO5 V I2C serial-control data-interface input/output SDIN131DI5 VPulldownSerial-audio data input 1 is one of the serial-data input ports. SDIN1 supports four discrete (stereo) data formats and is capable of inputting data at 64 Fs. SDIN230DI5 VPulldownSerial-audio data input 2 is o
7、ne of the serial-data input ports. SDIN2 supports four discrete (stereo) data formats and is capable of inputting data at 64 Fs. SDIN329DI5 VPulldownSerial-audio data input 3 is one of the serial-data input ports. SDIN3 supports four discrete (stereo) data formats and is capable of inputting data at
8、 64 Fs. SDIN428DI5 VPulldownSerial-audio data input 4 is one of the serial-data input ports. SDIN4 supports four discrete (stereo) data formats and is capable of inputting data at 64 Fs. VALID39DOOutput indicating validity of PWM outputs, active-high VBGAP10PBand-gap voltage reference. A pinout of t
9、he internally regulated 1.2-V reference. Typically has a 1-nF low-ESR capacitor between VBGAP and AVSS_PLL. This terminal must not be used to power external devices. VR_DIG33PVoltage reference for 1.8-V digital core supply. A pinout of the internally regulated 1.8-V power used by digital core logic.
10、 A 4.7-F low-ESR capacitor(3) should be connected between this terminal and DVSS. This terminal must not be used to power external devices. VR_DPLL17PVoltage reference for 1.8-V digital PLL supply. A pinout of the internally regulated 1.8-V power used by digital PLL logic. A 0.1-F low-ESR capacitor(
11、3) should be connected between this terminal and DVSS_CORE. This terminal must not be used to power external devices. VR_PWM48PVoltage reference for 1.8-V digital PWM core supply. A pinout of the internally regulated 1.8-V power used by digital PWM core logic. A 0.1-F low-ESR capacitor(3)should be c
12、onnected between this terminal and DVSS_PWM. This terminal must not be used to power external devices. VRA_PLL1PVoltage reference for 1.8-V PLL analog supply. A pinout of the internally regulated 1.8-V power used by PLL logic. A 0.1-F low-ESR capacitor(3)should be connected between this terminal and
13、 AVSS_PLL. This terminal must not be used to power external devices. VRD_PLL7PVoltage reference for 1.8-V PLL digital supply. A pinout of the internally regulated 1.8-V power used by PLL logic. A 0.1-F low-ESR capacitor(3)should be connected between this terminal and AVSS_PLL. This terminal must not
14、 be used to power external devices. XTL_IN20AIXTL_OUT and XTL_IN are the only LVCMOS terminals on the device. They provide a reference clock for the TAS5508 via use of an external fundamen- tal-mode crystal. XTL_IN is the 1.8-V input port for the oscillator circuit. A 13.5-MHz crystal (HCM49) is rec
15、ommended. XTL_OUT19AOXTL_OUT and XTL_IN are the only LVCMOS terminals on the device. They provide a reference clock for the TAS5508 via use of an external fundamen- tal-mode crystal. XTL_OUT is the 1.8-V output drive to the crystal. A 13.5-MHz crystal (HCM49) is recommended. (3)If desired, low-ESR c
16、apacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling capacitors of equal value provides an extended high-frequency supply decoupling. This approach avoids the potential of producing parallel resonance circuits that have been observed when par
17、alleling capacitors of different values. RadioFans.CN 61 TAS5508 Block Diagram PWM_HPP and MR PWM_HPP and ML MCLK XTL_OUT XTL_IN PLL_FLTM PLL_FLTP OSC CAP SCLK LRCLK SDIN1 SDIN2 SDIN3 SDIN4 SDA SCL RESET PDN MUTE HP_SEL BKND_ERR PWM Section PWM AP and Am7 Center PWM AP and AM4 R Rear PWM AP and AM3
18、L Rear PWM AP and AM8 Sub woofer PWM AP and AM1 L Front PWM AP and AM2 R Front Power Supply PWM AP and AM5 L Surround PWM L Lineout PWM AP and AM6 R Surround PWM R Lineout Digital Audio Processor VALID Control 8842 0 Det 88 PSVC 9 2 PSVC Volume Cotrol Clock, PLL, and Serial Data I/F Serial Control I
19、/F VR_PLL AVDD_PLL AVSS_PLL AVDD_REF VBGAP VRA_PLL VRD_PLL DVDD DVSS AVDD System Control DAP ControlPWM Control 8 8 Crossbar Mixer 7 Biquads DC Block De Emph SRC NS PWM 0 Det 7 Biquads DRC Loud Comp Soft Tone DC Block De Emph SRC NS PWM 8 2 Crossbar Mixer 0 Det 7 Biquads DRC Loud Comp Soft Tone DC B
20、lock De Emph SRC NS PWM 0 Det 7 Biquads DRC Loud Comp Soft Tone DC Block De Emph SRC NS PWM 0 Det 7 Biquads DRC Loud Comp Soft Tone DC Block De Emph SRC NS PWM 0 Det 7 Biquads DRC Loud Comp Soft Tone DC Block De Emph SRC NS PWM 0 Det 7 Biquads DRC Loud Comp Soft Tone DC Block De Emph SRC NS PWM 0 De
21、t 7 Biquads DRC Loud Comp Soft Tone DC Block De Emph Interpolate SRC NS PWM Soft Tone DRC Loud Comp Output Control Interpolate Interpolate Interpolate Interpolate Interpolate Interpolate Interpolate B0011-01 AVSS Soft Vol Soft Vol Soft Vol Soft Vol Soft Vol Soft Vol Soft Vol Soft Vol 8 TAS5508 8-Cha
22、nnel Digital Audio PWM Processor SLES091CFEBRUARY 2004REVISED AUGUST 2005 Figure 1-1. TAS5508 Functional Structure Introduction PWM13 RadioFans.CN 62 2. FL DISPLAY V.F.D (16-ST-103GINK) (FLT301) PIN CONNECTION GRID ASSIGNMENT RadioFans.CN 63 GRID ASSIGNMENT RadioFans.CN 64 RadioFans.CN 65 PARTS LIST
23、 OF P.C.B. UNIT zParts indicated by nsp on this table cannot be supplied. zThe parts listed below are only for maintenance. Therefore they might differ from the parts used in the unit in appearances or dimensions. Note: The symbols in the column Remarks indicate the following destinations. E2 :E2 mo
24、del EK : EK model PCB MAIN ASSY Ref. No.Part No.Part NameRemarksQty New SEMICONDUCTORS GROUP IC10100D2623077900IC TC74VHCU04FT J040740405580S IC102963243101310S IC,CPU MICRO PROCESS M3030RFGPFP FLASH(256K,12K) QFP100 8952109000010* IC103963239100780S IC,LINEAR-RESET NCP300LSN30T1 TSOP-5 J12503005001
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