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1、SERVICE MANUAL AV SURROUND RECEIVER MODELAVR-2106/886 TOKYO, JAPAN Denon Brand Company, D 1IN/LOW; 2IN) 31 R-Y1 INPUT 30 B-Y1 INPUT 29 Y1 INPUT 28 I2C GND 27 R-Y2 INPUT 26 B-Y2 INPUT 25 Y2 INPUT 24 23 22 21 20 19 18 17 16 15 SW GND ADRS SW R-Y/R OUTPUT B-Y/B OUTPUT Y/G OUTPUT SW Vcc (9V) SYNC Vcc (9
2、V) CP/HP INPUT Dig GND SCP OUTPUT DAC2 DAC1 fsc Y DL Y DL SW SW PEDESTAL CLAMP 1H DL CONTROL SECAM CONTROL CbCr / UV SW fsc TRAP OFFSET SW LPF / fsc TRAP BPFH. AFCH C / D 32fH VCO V C / D ACC TOF SCP SW APC P / N ID SYSTEM CW MATRIX TINT DEMO CHROMA BLK NOSE DET YUV RGB MATRIX CP / HP IN SW V SEP SY
3、NC SEP SUB-COLOR VCXO SUB- CONTRAST Y OFFSET SW DAC TEST Ys I2C BUS CONTROL PEDESTAL CLAMP PEDESTAL CLAMP HI: 20h/LOW: 24h 1 2345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 242526272829303132333435363738394041 42VDD VSS S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 GND CK DATA STB
4、 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 18 bit Latch Circuit (Rch) (Lch) Same as Rch Level Shift + Shift Register Circuit S2 S3 S4 S5 S6 S7 S8 S9 S10 S1 VDD STB DATA S2 S3 S4 S5 S6 S7 S8 S9 S10 GND CK Vss S1 13 14 1 3 4 5 6 7 8 9 10 11 12 2 15 16 28 27 26 25 24 23 22 21 20 19
5、 18 17 1 13 28 212 1227 14 15 16 Vss GND VDD S1S10 CK DATA STB GND=0V Vss=-8.0-17V GND=0V Border Input Pin No SymbolName Function Dual Power Use:VDD = 8.017 VSingle Power Use:VDD = 8.018V +Power Terminal Digital Ground +Power Terminal I/O Terminal Clock Input Low level Terminal Clock input for data
6、transfer. Serial input for switch setting. Strobe InputStrobe input for data writing.Strobe Input Data Input Input terminal of analog switch. TC9273N Terminal Function 1 2 3 4 5 6 7 8 9 10 11 12 13 1415 16 17 18 19 20 21 22 23 24 25 26 27 28VSS L-S1 L-COM1 L-COM2 L-COM3 ST GND VDD R-COM1 R-COM2 R-CO
7、M3 DATA CK L-S4 L-S2 L-S3 L-S5 L-S6 L-S7 L-S8 R-S1 R-S2 R-S3 R-S4 R-S5 R-S6 R-S7 R-S8 L-COM1 L-COM2 L-COM3 ST VDDVSS R-S1 R-S2 R-S3 R-S4 R-COM1 R-S5 R-S6 R-COM2 R-S7 R-COM3 DATA CK L-S1 L-S2 L-S3 L-S4 7 8 9 13 11428 27 24 19 18 17 16 15 2 3 4 L-S5 L-S6 L-S7 GND 20 21 22 23 25 26 5 6 10 11 12 L-S8 R-
8、S8 Level Shifter Latch Circuit Shift Register Level Shifter Latch Circuit RadioFans.CN 21 AVR-2106/886 LC74781 (IC1006) 1 2 3 4 5 6 7 8 9 10 11 12 VSS1 Xtal IN Xtal OUT CTRL1 BLANK OSC IN OSC OUT CHARA CS SCLK SIN VDD2 24 23 22 21 20 19 18 17 16 15 14 13 VDD1 RST CTRL3 CTRL2 SEP IN SEP OUT SEP C SYN
9、 IN VDD1 CV IN NC CV OUT CS9 RST23 VSS11 SIN11 SCLK10 OSCIN6 OSCOUT7 SYNIN17 SEPC18 SEPOUT19 CHARA8 VDD212 SEPIN20 CTRL322 4 CTRL1XtalINXtalOUTBLANKCVINCVOUTCTRL2 212351513 VDD124 Serial parallel converter 8-bits latch + command decoderHorizontal character size register Horizontal size counter Horiz
10、ontal display position register Horizontal dot counter Vertical display position register Vertical dot counter Blinking and inversion control register Blinking and inversion control circuit Blinking and inversion control register Blinking and inversion control register Character control counter Line
11、 control counter Timing generator Synchronization signal generator Character output control Background control Video output control Display control register RAM write adress counter Display RAM Vertical character size register Vertical size counter Decoder Font RAM Shift register Decoder Horizontal
12、character size register Horizontal character size register Horizontal character size register Horizontal character size register LC74781 Trminal Function Pin No.SymbolName 1VSS1GND 2Xtal INXtal oscillation 3Xtal OUTXtal oscillation 4CTRL1Xtal oscillation input switching 5BLANKBlank output 6OSC INLC
13、oscillation 7OSC OUTLC oscillation 8CHARACharacter output 9CSEnable input 10SCLKClock input 11SINData input 12VDD2Power 13CV OUTVIDEO signal output 14NC 15CV INVIDEO signal input 16VDD1Power 17SYN INSync. separate circuit input 18SEP CSync. separate circuit bias voltage 19SEP OUTComplex sync. signal
14、 output 20SEP INVertical sync. signal input 21CTRL2NTSC/PAL-M switching input 22CTRL3SEP IN input control 23RSTReset input 24VDD1Power (+5V) RadioFans.CN 22 AVR-2106/886 LH28F800BJE (IC805) LH28F160BJE (IC805) LH28F160BJE Block Diagram RadioFans.CN 23 AVR-2106/886 BA7626 (IC1000,1002,11501153) BU405
15、2BCF (IC601D,602D)MM74HC4053MX (IC1001,1004,1008) SN74LVC139A (IC820)74LVX157 (IC816) SN74LV573APW (IC818,819)SN74LV14APW (IC829) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Monitor OUT GND IN5 GND IN4 CTL E IN3 CTL D IN1 CTL A V OUT1 Vcc IN2 CTL B V OUT2 CTL C 6dB 6dB LOGIC LOGIC ABEMONITOR OUTCDEV OUT
16、1CDEV OUT 2 LL*IN 1LL* LL*IN 1 HL*IN 2HL*IN 2HL* LH*IN 3LH*IN 3LH*IN 3 HHLIN 4HHLIN 4HHLIN 4 HHHIN 5HHHIN 5HHHIN 5 Note 1: * mark means that feasible for either H or L. Note 2: Each input terminal is provided with sink chip clamp (BA7625). Each input terminal takes 20kohm at the end (BA7626). Y4 Y2
17、Y3 Y1 INH VEE Vss VDD X2 X1 X0 X3 A B Common X 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 INHABON SWITCH LLLX LHL LLH LHH HXX Y00 XY11 XY22 XY33 NONE FUNCTION TABLE TOP VIEW X:Dont Care X0 Y0 X1 Y1 X2Y2 X3 Y3 Common Y INH VEE B OUT/IN A OUT/IN X Y 1 2 VEE 3 4 5 6 7 89 10 11 16 15 14 13 12 Y1 Y0 Z1 Z Z0
18、Enable GND Vcc Y X1 X X0 C A B X = Dont Care Truth Table Control Inputs Select Enable C B A ONSwitches L L L L Z0 Y0 X0 L L L H Z0 Y0 X1 L L H L Z0 Y1 X0 L L H H Z0 Y1 X1 L H L L Z1 Y0 X0 L H L H Z1 Y0 X1 L H H L Z1 Y1 X0 L H H H Z1 Y1 X1 H X X X None 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1G 1A 1B
19、1Y0 1Y1 1Y2 1Y3 GND VCC 2G 2A 2B 2Y0 2Y1 2Y2 2Y3 FUNCTION TABLE (each decoder/demultiplexer) INPUTS OUTPUTS G SELECT OUTPUTS G BAY3Y2Y1Y0 LLLHHHL LLHHHLH LHLHLHH LHHLHHH HXXHHHH 1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Vcc ST 4A 4B 4Y 3A 3B 3Y SELECT 5 SEL 1 2 3 4 5 6 7 8 10 9 20
20、 19 18 17 16 15 14 13 12 11 OE D0 D1 D2 D3 D4 D5 D6 D7 GND Vcc Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 LE D Q L D Q L D Q L D Q L D Q L D Q L D Q L D Q L D0D1D2D3D4D5D6D7 L E OE 1 23456789 11 1213141516171819 Q0Q1Q2Q3Q4Q5Q6Q7 1A 1Y 2A 2Y 3A 3Y GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 Vcc 6A 6Y 5A 5Y 4A 4Y RadioFans.CN
21、24 AVR-2106/886 PCM1791ADBR (IC205X) PCM1791 Terminal Function DESCRIPTIONS Pin No. Pin Name 1LRCKI Left and right clock (fs) input for normal operation. WDCK clock input in external DF mode. Connected to GND in DSD mode* 2BCKIBit clock input. Connected GND for DSD mode* 3DATAI Serial audio data inp
22、ut for normal operation. L-channel audio data input for external DF and DSD modes* 4MUTEI Analog output mute control for normal operation. R-channel audio data input for external DF and DSD modes* 5SCKIISystem Clock Input. BCK (64fs) clock input for DSD mode* 6RSTIReset* 7VDDDigital power supply, +3
23、.3 V 8DGNDDigital ground 9AGNDFAnalog ground (DACFF) 10VCCRAnalog power supply (R-channel DAC), +5.0 V 11AGNDRAnalog ground (R-channel DAC) 12VOUTR-OR-channel analog voltage output- 13VOUTR+OR-channel analog voltage output+ 14VCOMInternal bias de-coupling pin 15VCCCAnalog power supply (internal bias
24、), +5.0 V 16AGNDCAnalog ground (internal bias) 17VOUTL+OL-channel analog voltage output+ 18VOUTL-OL-channel analog voltage output- 19AGNDLAnalog ground (L-channel DAC) 20VCCLAnalog power supply (L-channel DAC), +5.0 V 21VCCFAnalog power supply ( DACFF), +5.0 V 22ZEROROZero flag for R-channel 23ZEROL
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