Arcam-DV78-dvd-sm维修电路图 手册.pdf

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1、DiVA Service Manual DV78 DVD Player Issue 1.0 ARCAMARCAM Bringing music +5VD is used for all 5v Digital/Video supplies the +12VD is used for Scart switching. Diva Dv78 circuit description RadioFans.CN The 1V8 rail is derived from the 3V3 rail and is regulated by the adjustable regulator at location

2、REG1003. The Analogue supply stages arrive at the main board as +15V3 and 15V3 rails these are filtered L1002 and L1015 before being regulated by the adjustable regulators at locations REG1000 and REG1002 to provide +/- 12V rails for the Analogue output stage. Regulator REG1001 is fed from the +15V3

3、 rail and forms the Audio DAC supply. The Display board requires several supply voltages these are simply passed through the main board, being filtered on the way to prevent transmission of noise through to the surrounding electronics. The display takes the +5V, -19V, -13V5 and -9V the 13V5 and 9V f

4、orm a floating 4.5V supply biased relative to the 19V grid voltage. Display Board The main component of the Display board is IC1 this is a Vacuum Florescent Display driver with keyboard san and a serial data in/out interface. The Chip receives display drive serial data from the Vaddis V chip on the

5、main board via Con1 on pins 12, 13 and 14 these will be seen a DIN, STS and CLK this data is used to drive the VFD a DOUT line interfaces with the VADDIS V and supplies Keyboard Scan information. The keyboard scan is a 6 x 4 matrix with the Key Source appearing at S3, S4, S5, S6 and the Keyscan data

6、 returns appearing a K2, K3 and K4. Please see: above for power supply information. The Infra red pick-up at location RXI receives RC5 data and send the data to the Vaddis V on the main board via transistors TR2 and TR3, LED 2 is used to mix the rear panel RC5. The rear panel 3.5mm input jack receiv

7、es modulated RC5 code; this is filtered for ultra sonic noise by the inductors at locations L900 and L901 and then passed to the Infrared diode on the display at location LED2. Main Board electronics DV78. Zoran Vaddis V. The main processor/control chip on the main board is the Zoran Vaddis V at loc

8、ation IC202, this is the latest incarnation of the very popular Vaddis range of processors and allows for a much lower component count when compared to our earlier players as many of the playback functions have moved onto the Vaddis V silicon. Below you will see the major functions of the Vaddis V w

9、hen used with the DV78. o Decoded Analogue Video output (internal DAC) used on the DV78 only. o SPDIF output. o Internal display interface. o Internal ATAPI interface. o Internal IR interface. o Serial in/out for RS232 (Optional). A more detailed explanation of the Vaddis V and peripheral components

10、 follows. Vaddis Power The Vaddis V is powered by two separate supplies the Vaddis requires a 1.8v supply for the core, this is regulated from the 3.3v rail by REG1003, the 3.3v rail is used to supply power to the I/P O/P ports of the chip. ATAPI interface CON203 is an ATAPI interface on a 40 way ID

11、E connector. This is decoupled from the Drive via an array of decoupling resistors as required by the ATAPI spec. RadioFans.CN Display Board interface The display board interface is on the 16 way FFC flexi foil connector at location CON202. Power for the display also travels on the connector. There

12、are 4 wires to interface with the VFD driver chip these are seen as. o XFPDIN - Data to the display board o FPDOUT - Data from the display board o XFPCLK - Clock o XFPSEL - Chip select The above control lines are level shifted to 5v logic from 3.3v levels by IC200 (74HCT125) these are the levels req

13、uired by the VFD drive chip. The IR output from the Display board arrives as IRRCV this is an open collector signal, which can be wire-Ord with the re-panel remote input. Digital Audio The Digital audio leaves the chip as 1 data line labelled as. o ADAT0 - Left and Right channel data Along with the

14、ADAT line we will also see the ABCLK and ALRCK as required for IS2 data conversion. The Vaddis V also supplies a direct SPDIF output for interfacing with ancillary processing equipment. Flash/ SDRAM IC203 is a 64Mbit (32 bit x 2Meg) SDRAM. It runs at 135MHz IC205 is a 16Mbit (16 bit x 1Meg) intel ty

15、pe flash IC for program storage (Player software). The flash interfaces to the Vaddis V using the SDRAM bus it may appear that the bus connects to the flash in a random manner, however this is simply because the Vaddis bus is multiplexed that way. The Flash will be accessed at power up and the conte

16、nts are copied to the SDRAM the program will then be run from the SDRAM. Series resistors are employed to isolate the flash bus from the main SDRAM bus. EEPROM IC204 is a 8kBit (1K x 8) Serial EEPROM. This is used for storage of non-volatile storage of player settings, region settings and bookmark d

17、ata. Clocks CLK27MV is the 27Mhz clock for video. It is used to generate the 135Mhz clock for the Vaddis microprocessor and DSP. The MCLKV is the audio master clock for the Vaddis. We run the Vaddis in PLL bypass mode and generate or own master clock (see main clock section of manual) for higher acc

18、uracy and improved performance across Audio and Video. RESET IC201 is a reset generator chip that monitors the +3.3V rail and ensures a reset signal PWR_ON_RESET* is generated on power up, or if the mains power dips below an operational level. This signal is used to reset the Vaddis V and Flash micr

19、o only. The Vaddis V line labelled as RESET* resets the remaining circuitry of the player apart from the HDMI chip, this has its own reset line labelled as HDMI_RESET this is necessary if we require to reset the HDMI chip only (for example when the HDMI sink is connected and then disconnected). Seri

20、al Port The VADDIS V can interface with the external world via the RS232 connector at location CON900 and the RS232 Transceiver at location IC900, the serial data lines are shown as SERIAL RX and SERIAL TX these lines allow for direct control over the unit via RS232. Fig 2. GPIO control signals from

21、 the Vaddis V Single Name I/P-O/P Function PSUFSO-1 Output Control PSU Clock divider ENABLE_AV Output SCART control High in normal operation and low in standby 16/9 Output Scart 16/9 anamorphic control line GAIN_SCALING Output High for HDCD gain scaling ML_8740_0-2 Output SPI load signal for Audio D

22、ACs 0 MC Output SPI clock signal for DAC control MD Output SPI data signal for DAC control FSELE0-1 Output Frequency select generator MUTE* Output Active low audio mute signal RESET* Output System reset RadioFans.CN Clocks and SPDIF stage. IC300 is a PLL1700E clock generator IC the chip is powered f

23、rom the +5V(D) rail. The Chip runs in software mode and is slaved from the Vaddis V (data coming in on the MD line). X300 is a 27Mhz crystal that IC300 uses to generate all the video and audio clocks required by the system the crystal sits on the XTI and XTO pins of the chip, the 27Mhz output at Pin

24、 10 (MCKO) is used to drive the Vaddis chip directly bypassing the internal PLL. The frequency of the audio master is dependent on the on the current audio sample rate (I.e the sample rate required by the format CD=44.1Khz and DVD=48khz etc) and this is set by the system micro via the MD, MC and ML_

25、1700 lines from the Vaddis V. Clock Buffer IC301 us used to buffer the audio master clock. The circuit is arranged so that each device that requires the audio master clock has its own driver these are seen as. o MCLK_DAC0 - Pin 18 o MCLK_DAC1 Pin 16 o MCLK_DAC2 Pin 14 o MCLK_VADDIS Pin 3 o MCLK_HDMI

26、 Pin 9 We also run the Mute Line from the Vaddis V IC301 this can be seen on Pin 12 and drives transistor TR401, the transistor pulls the relays RLY400, RLY500, RLY600 to ground and un-mutes the audio outputs. IS2 Audio Data IC302 and IC309 are buffers for the 12S signals these ensure that the signa

27、ls travelling to the DACs are point to point. IC302 deals with the ALRCK and ABCLK and IC309(NF DV78) the ADAT0,1,2 all signal are split into three separate lines for the three stereo DACS. PSU Clock Divider IC304 a/b form a clock divide by 1, 2 or 4 to ensure the PSU clock is always either 44.1kHz

28、or 48Khz (See fig 1 within the power supply description section). The circuit is fed from the ALRCLK (Audio clock) the selected PSUCLK is controlled by PSUFSO and PSUFS1. The output of the PSU circuit can be seen to leave IC305 on pin 5 via R311. Please see Fig 1 for PSU control information. The cir

29、cuit will also switch the PSUCLK off when switching between sample rates (the PSU will free run when the PSUCLK is not present). SPDIF Output The SPDIF output consists of IC901 implemented as a inline buffer and parallel output buffer. Gate A buffers the signal so that the SPDIF line from the VADDIS

30、 sees fewer loads and form a feed to the Optical output transmitter, gates B,C and D drive the SPDIF in parallel so that we can drive a 75ohm load adequately. The resistors at the output of IC901 are arrange so that the output will be 500mV pk- pk when the output is terminated with a 75 ohm load at

31、the same time the output impedance of the circuit is 75ohms as required by the Sony Philips Digital Interface specification. Left and Right channel D to A stages The Wolfson WM8740 stereo DAC ay location IC403 requires +5V(A) and a +3V3 supply along with the Digital Audio data lines already describe

32、d in this guide. The Left channel output only will be described in this section. IC400B and associated components form a 2nd order Bessel filter with a differential input and a gain of 1 this follow by a output buffer IC401B, the gain of IC401B is control by the switching chip at location IC402, in

33、normal use the Gain of IC401B is set to 1.1 but in HDCD mode the IC402 switches a second 10k resistor in parele with R413 and the gain is set to 2.2 allowing for the higher audio output required by the HDCD standard. C436 is an A.C coupling capacitor used to remove the few mV of offset that the DAC

34、produces; D400 provides protection against from ESD. The all output relays are under control of the Vaddis V chip but will also mute the outputs instantly under mains failure conditions. Switching drive is provided by TR401 (MUTE_BUF) and TR400 (AC_PRES) the relays are in mute mode if either the inp

35、ut to TR401 is Low or if the input to TR400 is high. Please note: The Scart left/right audio is fed from the outputs of the left/right audio stages. RadioFans.CN Video Output stage The DV78 video output stage makes use of the VADDIS Vs on board video DAC stages and as such does not use the superior

36、Analogue devices video encoder DV79/DV29 and is fed by the following video lines from the Vaddis V. o Composite o SVID_C o SVID_Y o V or Red o U or Blue o Y or Green If we look at the Composite stage only, we will see that the Analogue video signal is filtered by C710, C711 and L705 before being pas

37、sed through the Video Op- amp at location IC701 the output is decoupled by capacitor C738 before reaching R714 this forms the 75 ohm load required. All other video outputs are identical. SCART Output RGB and Composite video signals as well as Left and right audio signals are all present on the SCART

38、 output socket. As the RGB and YUV signals share the same output port at the Vaddis V the player must be set to RGB SCART operation to have a RGB output on the SCART. Please note: When in RGB SCART mode the RGB does not contain a Sync signal and the sync must be taken from the Composite out (4 wire

39、RGB). Also present at the Scart are a number of control flags for the monitor these include 2 GPIO control lines direct from the Vaddis. o ENABLE_AV o 16/9 These are seen at the SCART output pins as. o O/6/12 o RGB STAT The 0/6/12 line (SCART pin 8) is used to inform the monitor of the screen format

40、 being sent by the player as set in the video set-up section of the software. o Standby = 0V o 16:9 aspect ratio = 6V o 4:3 aspect ration = 12V The RGB status line (SCART pin 16) will be seen as 0v = no RGB and 1v is RGB present. RadioFans.CN ISSUE DRAWING NO. DRAWING TITLE DATE Filename: ECO No.DES

41、CRIPTION OF CHANGE L959_1.1.sch DV78 SERIES PSU Contact Engineer: L959CT 22-Apr-2004 INITIALS Printed:11Sheetof Notes: Contact Tel:(01223) 203200Kevin Lamb A & R Cambridge Ltd. Pembroke Avenue Cambridge CB5 9PB Waterbeach ? DGND DGND DGND DGND DGND VN35V6 VN35V6VN35V6VN35V6 DGND 115V 115V 6 4 2 1 5

42、3 7 TX1 Small Toroidal Mains L924TX D1 2KBP02 VN35V6 DGND 1 2 3 4 5 6 CON1 MOLEX 44472 L N E SKT1 BULGIN PX0580 C2 C1C3 3N3 250V CER C4 3N3 250V CER 1 3 4 2 L1 250U SW2A SDDFC30400 SW2B SDDFC30400 1A 1 1B 2A 2 2B 115V230V SW1 18-000-0019 FHLDR2 20mm HLDR FHLDR1 20mm HLDR FS1 T315mA S504 FS2 T315mA S

43、504 VN19V EMC Shield SH1 1 2 3 4 CON5 Amp HD Pwr Con VP5V VP12V DGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CON7 MOLEX 52045 VN19V VN13V5_F1 VN9V_F2 DGNDAGND VP12V VP15V5 VP5V VP3V3 VP3V3 VN15V5 VP5V VP3V3 VP3V3 VP3V3 VP3V3 VP5V SPARE3 SPARE4 AC_PRES*

44、PSU_CLK DGND VP3V3 VP5V SPARE1 SPARE2 C46 470UF 25V YK C39 220UF 16V YXF C54 1000UF 16V YXF C55 1000UF 16V YXF C45 470UF 25V YK C44 470UF 25V YK D4 UF4003 DO-41 C34 1N0100V CER C36 1N0 100V CERC25 100N 100V MKS2 C20 100N 100V MKS2 C22 100N 100V MKS2 C21 100N 100V MKS2 C23 100N 100V MKS2 C26 100N 100

45、V MKS2 C24 100N 100V MKS2 C19 100N 100V MKS2 C18 100N 100V MKS2 R31 10R 0W25 MF R18 10R0W25 MF R22 470R 0W25 MFDZ5 BZX79C 5V1 DO-35 TR6 BD179 TO-126 R24 33R0W25 MF R5 4K70W25 MF C40 220UF 16V YXF C17 100N 100V MKS2 DZ6 BZX79C 12V DO-35 R11 9K1 0W25 MF R7 6K8 0W25 MF R4 4K70W25 MF R26 68R 0W25 MF R27

46、 2K7 0W25 MF R25 100R 0W25 MF R28 22R 0W25 MF R15 10K 0W25 MF C50 22N100V MKS2 C16 100N 100V MKS2 C56 4N7 100V CER TR8 BC556B TO-92 M1 IRF640N TO-220 C6 100N 100V MKS2 C7 100N 100V MKS2 COMP 1 VFB 2 ISEN 3 RT/CT 4 GND 5 OUT 6 VCC 7 VREF 8 IC1 UC3843AN DIP-8 TR7 BC556B TO-92 DGND TR3 BC546B TO-92 R13

47、 10K 0W25 MF VP5V PSU_CLK C35 1N0100V CER R19 10R0W25 MF C33 1N0100V CER R23 33R0W25 MF AGND C41 470UF 25V YK C9 100N 100V MKS2 C10 100N 100V MKS2 C12 100N 100V MKS2 R20 470R 0W25 MF D2 UF4003 DO-41 C42 470UF 25V YK C13 100N 100V MKS2 D3 UF4003 DO-41 C11 100N 100V MKS2 VP15V5 VN15V5 VN13V5_F1 VN9V_F

48、2 VP5V VP3V3 VP12V VN35V6 R3 4K7 0W25 MF TR2 BC546B TO-92 R6 6K8 0W25 MF C31 22UF 63V YK VP5V DGND AC_PRES* R9 1K00W25 MF TR4 BC546B TO-92 C47 22P 100V N150 DGND R8 1K0 0W25 MF C14 100N 100V MKS2 R10 1K00W25 MF C15 100N 100V MKS2 VN35V6 5V_NFB 3V3_NFB 3V3_NFB 5V_NFB C51 22N 100V MKS2 L6 6U82.1A 8RHT

49、2 L7 6U82.1A 8RHT2 L5 33U 1.17A 8RHT2 L3 33U 1.17A 8RHT2 L4 33U 1.17A 8RHT2 VN35V6 VN35V6 VN13V5_F1 C29 22UF 63V YK MAINS SUPPLY FOR EXT. AUDIO SUPPLY TX C49 22N 100V MKS2 R14 R29 82K0W25 MF NF NFB (To Controller E/A) (NFB From PSU Outputs) GREY 4 DK GREY 3 LT GREY 2 BLUE 1 CON2 WAGO 256 GREY 2 GREY 1 CON4 WAGO 256 GREEN