Arcam-AV8-avr-sm维修电路图 手册.pdf

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1、AV8 FMJ AV8 Preamp Processor Service Manual ARCAMARCAM Issue 2.0 RadioFans.CN Contents List Section Issue Manual Updates ! Service Manual changes issue 1.0 to 2.0 - Technical specifications ! Front main, zone2 and two tape loops “Tape” and ”VCR”. Main and zone2 outputs have volume controls (either o

2、f which can be the source for the on-board headphone amplifier). A gain ranging stage in the middle of the audio path sets the headroom of the signal chain and also provides a feed to the A-D converter on the digital board. Control of the board is via the host micro-controller on the digital board.

3、BLOCK DIAGRAM 2 2 2 2 2 2 2 2 2 2 2 Input Mux Record loop buffers Volume Volume Volume Gain range Mute Mute Headphone select Mute ZONE2 MAIN L/R Surround/ Centre/ Sub outs Headphone Stereo inputs Internal DAC L/R External SACD input L/R Internal DAC Surround /Centre / Sub channel inputs External SAC

4、D Surround /Centre / Sub channel inputs Tape out VCR out Headphone amp 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 6 6 6 6 Multichannel Mux To ADC Key: n Signal bus where n is the number of audio channels RadioFans.CN Input switching Refer to circuit diagram L921 sheet 1 The 24 off 74HCT4053 analogue

5、multiplexers route the various analogue inputs to the four output mix buses:- ! VCR ! Tape ! Analogue ! Zone2 The main stereo inputs have 100pF NP0 capacitors to ground to reduce any high frequency signals radiating from the input cables which are connected to the unit. This is an EMC preventative m

6、easure. In addition to be able to select any particular input as the source, the input impedance of each input connector was required to remain constant regardless of whether it was selected or not. Input selection is therefore performed using a method called “virtual earth mixing”. Each input can b

7、e switched to one of the four stereo busses via an input resistor, or switched to ground For simplicity consider only the main ANALOGUE L MIX bus. Each input is fed onto the common bus via a resistor and an electronic switch. The bus is the input to an op-amp in an inverting configuration. The switc

8、h either allows the signal through to the op-amp, or shunts it to ground. The inverting input of an inverting configured op- amp effectively behaves as a ground (hence “virtual earth”), which is why the input impedance looks the same regardless of the state of the switch. In theory all inputs can mi

9、x into the op-amp simultaneously, but the control software only allows one input switch to connect to the op-amp at a time. If multiple inputs can be heard simultaneously then there may be a problem with the control logic (see L921 circuit sheet 7), or the AUD SDATA line from the Digital board may b

10、e latched high. For the “ANALOGUE L MIX” and “ANALOGUE R MIX” buses, the resistor is 15k, for the other three buses, the value is 100k. The three 100k in parallel with 15k give a total input impedance of just over 10k - the minimum required for THX certification. These particular values were chosen

11、to maximise the noise performance of the main stereo ANALOGUE L/R MIX buses, bearing in mind that a larger value resistor has poorer noise performance. The 100k resistors feed into the op-amps of the less critical audio paths for ZONE2 and the record loops VCR MIX and TAPE MIX. Input gain range Refe

12、r to circuit diagram L921 sheet 3 The gain ranger sets the headroom for the A-D converter (on the digital board) and for the rest of the analogue chain. The aim is to set the gain such that clip is not quite reached with the input of the unit receiving a maximum signal. Excessive headroom reduces si

13、gnal-to-noise performance unnecessarily. Left and right channels are identical, therefore only the left channel will be described. IC301A is the op-amp into which the input resistors feed (described in Input switching above). R302 in the fixed feedback path ensures the op-amp cannot go open loop, ca

14、using it to latch into a power rail. C301 compensates for small stray capacitances at the op-amp input, ensuring it does not oscillate. Switching in R303, R304, R305 or any combination in parallel with R302 sets the closed loop gain with reference to the 15k input resistor. IC302 selects which of th

15、e three resistors are in circuit. It is controlled by the micro via control line demultiplexer IC707. Several ranges, nominally +6dB, 0dB, -6dB and - 12dB can be generated depending on the state of the GAIN RANGE lines A,B the on screen display chip for the main zone 1, the input multiplexer for the

16、 onscreen display chip to select which type of video source to send to the OSD, the clock oscillators for PAL and NTSC generation, the clock multiplexer to select PAL or NTSC for each of the zones, the RGB output buffers and sync on green insertion, a sync separator and mono-stable to generate a bla

17、ck level clamp signal. IC301 selects the input signal from the composite, S video or Y/G inputs, this signal is buffered by Q300 divided by two by the two 75R resistors then AC coupled into the input of the On Screen Display chip IC302. It is also possible to route the output of the OSD chip itself

18、via this multiplexer to the input of the sync separator so that the black level clamp can still operate when the OSD chip is generating RGB or YUV signals. IC302 is the On Screen Display chip it generates the text patterns which are multiplexed into the video using the fast blanking signal. Fast bla

19、nking is asserted whenever there is activity on the output of the OSD chip. The chip is programmed via a serial bus made up of the lines Video serial data, Video serial clk and Video serial cs. The Horizontal line lock is performed by a Phase Locked loop internal to the OSD chip the filter component

20、s for which are R349, C349 and C350. LESCREEN input sets the screen intensity for the background and LECHAR sets the Screen intensity for the Characters. The potential dividers on the pins define the voltages. The composite output of the OSD chip is sync tip clamped by the circuit made up of Q302 Q3

21、04 and D300. This circuit pulls the most negative part of the signal to a fixed voltage, in this case approximately 0v. The sync tip clamp works in the following way. A fixed voltage of approximately 1.2v is generated by D300 and the 4K7 current limiting resistor R343, this holds the base of Q304 at

22、 1.2v which in turn holds the base of Q302 at 0.6v. If the voltage on the collector of Q302 goes 0.6 v below the voltage on the base (i.e. below 0v) the darlington pairQ302 and Q304 turns on and dumps charge on the coupling capacitor C348 until the voltage is increased to 0v. So the most negative pa

23、rt of the signal always remains at 0v, the most negative part of a composite video signal is the sync and hence this is pulled to 0v. This sync tip clamp circuit is used for all of the composite signals so they are all clamped to the same level. This RadioFans.CN means that when the output of the OS

24、D is switched into the output the DC level does not change avoiding any flickering or brightness changes. The Y output is clamped to 0v at its sync tip by the transistor Q301. This is an active clamp that pulls the DC level to 0v every time a sync pulse occurs. The clamp signal is created from the c

25、omposite sync stripped by the OSD chip IC302 this is the shortened to a 700nS pulse by the mono stable IC308. The time of the pulse created by IC308 is set by R310 and C304. The clamp signal is also used to clamp the incoming Y signal of both S video and YUV signals. It is also used when the system

26、is running in RGB mode to clamp the RGB signals to black level. The RGB output is used when the system is operating in RGB mode and creates the colour information for the text being inserted. The level is reduced from TTL levels to video levels by the potential dividers that feed into video buffers

27、made from the opamps IC300 and IC303. A sync signal can be added to the green output by activating the output of the AND gate IC502. This raises the DC level of the whole signal by 300mV then introduces 300mV syncs to 0V. The PAL and NTSC clocks are generated by the CMOS oscillators. The oscillator

28、is made by applying feedback around un-buffered 74HCU04 inverters. The oscillation is then buffered and amplified by some of the extra gates left in the 74HCU04 pack. Both oscillators run at all times so that the system can cope if Zone 1 is running NTSC and Zone 2 is running PAL. Which clock is use

29、d for the zone 1 and zone 2 OSD chips is controlled by the Tri-state buffers in IC305, these form a low noise 2:1 mux for the clocks. RC5 I/O Triggers and RS232 Refer to circuit diagram L922 sheet 5 Sheet 5 has two RC5 demodulators made using IC400 and IC401, one RC5 mixer and buffer, two 100mA curr

30、ent limited trigger outputs, the RS232 output connector and the program button for reprogramming the Flash memory in the micro controller. YUV/RGB Video Mux and OSD insert Refer to circuit diagram L922 sheet 6 The circuit on this sheet multiplexes between the three RGB/YUV inputs using the high spee

31、d multiplexers IC503 and IC505. Once the signal has been selected it is AC coupled and DC restored using the active clamps Q511,Q500 and Q512. (operation of this clamp is described on sheet 4). The multiplexer following the DC restore IC506 inserts text using the fast blanking signal from the OSD ch

32、ip. IC506 has a gain of 2 and 75R output capability to drive the output directly. The type of signal that is inserted (RGB or YUV) is selected by the mux chip IC500A. The mux can select the signals from the RGB buffers on Sheet 4 for RGB operation or the Y output of the OSD chip and DC levels genera

33、ted by the potential divider R519, R500 and R520,R522. These DC levels generate a blue background for the text when it is not being overlaid on the incoming video. IC501 switches between the blue background levels and zero volts the signal CHAR OUT is active when a character is present on the output

34、 and it is this that switches IC501. The OSD B and OSD G signals are In a logical AND with the Char Out signal to switch between blue & white colour. When the circuit is set to blue output, no green output & no char the colour is set to blue i.e it is back ground. In any other condition the colour i

35、s set to white because it is a character i.e text is being displayed. Zero volts is used when inserting characters as this provides a colourless background. I.e. the characters are white on a blue background. Q503, Q504 and Q505 are used to mute the RGB output of the unit when it is not in use and a

36、t power up. SPDIF MUX and RXTX Refer to circuit diagram L922 sheet 7 The circuit on this sheet multiplexes the seven SPDIF inputs to a single line that is buffered and passed to the digital pcb. The input signals are 75 R terminated then AC coupled into the multiplexer. The multiplexer is made up of

37、 The 2:1 CMOS switches IC600 IC601 and IC602. The multiplexer works in the same way as the audio multiplexers. It switches the signal between the input to the buffer circuit and a DC level at half the rail i.e. 2.5V. Each multiplexer has a independent select line, only one multiplexer should be sele

38、cted at a time as the circuit will mix the signal together if more than one is selected. After the input signal has been selected by the mux it is buffered and amplified by IC603. Applying feedback around a 74HCU04 biases it into the linear region. The three stages amplify the 0.5V P-P SPDIF signal

39、up to a 5V logic level. Two outputs are buffered off of this logic level, one to go to the digital board the other is used for the digital record loop. The digital record output is driven by IC605 either the buffered output of the input mux or the SPDIF output of the DSP (from the ADC input) can be

40、selected. The signal is select by the lines SPDIF LOOP and SPDIF ADC TX. The 75R characteristic impedance is formed from the parallel combination of R613 100R, R626 680R and R627 680R. The digital output is AC coupled. Control of all of the select lines for the Multiplexers and Buffers is handled by

41、 IC604 and IC606. IC604 and IC606 are latched serial to parallel converters. SVIDEO and CVBS OSD insert Refer to circuit diagram L922 sheet 8 The circuits on this sheet switch the OSD generated test into the incoming video. IC700 is the fast video switch that inserts the text, it is controlled by th

42、e fast banking signal directly out of the OSD chip. IC700 has a gain of 2 and can drive 75R loads. The composite video signal is sync tip clamped at the input to the switch by Q701 and Q705 this works in the same way as the Sync tip clamp on sheet 4 that operates on the composite signal out of the O

43、SD chip. These two sync tip clamps ensure that the DC level is the same at the input to the switch so that the text is switched in at the correct DC level. The S-video Y input is actively clamped by the clamp signal as described on sheet 4. This ensures that the two S- video Y inputs, one from the i

44、nput source and the other from OSD, are at the same DC level. Ensuring the DC levels are correct means the text can be inserted at the correct level. RadioFans.CN The S-video C and OSD C signals do not need a DC clamp as they will float to the same level due to the nature of the signal. S-Video Mult

45、iplexer Refer to circuit diagram L922 sheet 9 This contains the multiplexing for the S-Video signals. It operates in the same way as the composite multiplexer (Sheet 3 Video board) except two multiplexers are used for each signal to carry the independent Luma and Chroma signals. IC800 and IC807 carr

46、y the main feed Luma and Chroma respectively. IC801 and IC806 carry the VCR record loop Chroma and Luma respectively. The Main feed is buffered by IC803 it then goes to the OSD insert sheet, the VCR output is buffered by IC802 and then output to the VCR connector. Control of the Multiplexer is via s

47、erial to parallel shift registers IC804, IC805 and IC808 these also have the control lines for the SCART control signals, sync on green and the Mute signals. Zone 2 OSD Refer to circuit diagram L922 sheet 10 This contains the OSD sync stripper and OSD insert circuits for Zone 2. It works in a very s

48、imilar way to the circuits on sheets 4 and 8 combined together. As Zone 2 only operates in composite the circuit is without the extra multiplexing for S-Video and Component signals. The Zone 2 video comes from the video input sheet 3 buffer it is terminated on this sheet then fed to both the OSD chi

49、p IC900 and the OSD insert multiplexer (Pixel Switch)IC902. Characters are generated by the OSD and this signal is present on the second input to the pixel switch. Both of the signal are sync tip clamped by transistors Q900, Q901, this means that their DC levels at the input to the pixel switch should be about the same. The fast blanking signal from the OSD controls the position of the pixel switch. Fast blanking is high when OSD characters are being generat