Kenwood-RXDV-555-H-Service-Manual电路原理图.pdf
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1、70%MINI HiFi COMPONENT SYSTEMRXD-V555/V555-H/V757SERVICE MANUAL2001-10 PRINTED IN KOREAB51-5764-00 (K/K) 404 *Refer to parts list on page 28. In compliance with Federal Regulations, following are repro-duction of labels on, or inside the product relating to laserproduct safety.KENWOOD-Corp. certifie
2、s this equipment conforms to DHHSRegulations No.21 CFR1040. 10, Chapter 1, subchapter J.DANGER : Laser radiation when open and interlock defeated. AVOID DIRECT EXPOSURE TO BEAM.Dress ring (A21-3957-08)FRT cab assy *(A60-)Front glass *(B10-)Panel(VCD)(A60-2220-08)Knob(VOLUME)(K27-2470-08)Cassette lid
3、(R)(A21-3959-08)Phone jack (E11-0942-08)Cassette lid(L) (A21-3958-08) Jack(MIC) (E11-0953-08)*Refer to page 2 if you want to know system configuration.(XD-V555/XD-757)*Knob(MIC VOLUME) (K29-8153-08)AC Plug Adaptor (1)(E03-0115-05) Use to adapt the plug on thepower cord to the shape of thewall outlet
4、.(Accessory only for regions whereuse is necessary.) AM Loop Antenna(1)(T90-0879-08)“AA“ size battery(2)(UM/SUM-3, R6, HP-7 or similar) Remote Control(1)(A70-1574-08)FM Antenna(1)(T90-0883-08)Video Cable(1)(E30-7255-08)RXD-V555/V7572CONTENTS / ACCESSORIESCONTENTS / ACCESSORIES.2EXTERNAL VIEW.3ADJUST
5、MENT.7PC BOARD.8SCHEMATIC DIAGRAM.16EXPLODED VIEW.26PARTS LIST.28SPECIFICATIONS.Back coverContentsAccessoriesSYSTEMMAIN UNITDESTINATIONSPEAKERXD-V858RXD-V757MILS-N90VSXD-V757RXD-V757MILS-N70VSXD-V555RXD-V555MILS-N50VSXD-V555-HRXD-V555-HMLS-N50VS-HSystem ConfigurationsThe marking of products using la
6、sers(Except for some areas)The marking is located on the rear panel andsays this product has been classified as Class1. It means that there is no danger of hazard-ous radiation outside the productCLASS 1LASER PRODUCTCautionsRXD-V555/V7573EXTERNAL VIEWANTENNAAM LOOPFM75VIDEO/AUXVIDEOOUTSPAN SELECTOR2
7、30V240VFM 50kHz AM 9kHz FM 100kHz AM 10kHz +-LSPEAKERSRATED SPEAKER IMPEDANCE:6 OHMS MIN.RLRCabinet(TOP) (A02-3014-08)AC power cord (E30-7227-08)RCA socket(E02-0021-08)Lock terminal board(E70-0144-08) FM Antenna (E70-0145-08)Switch(S62-0086-08)Pin jack(E63-1219-08)AC power cord bushing (J42-0338-08)
8、Pin assy (E40-8933-08)RXD-V252/V252-H4CIRCUIT DESCRIPTIONBlock Diagram for MPEG1 Video/Audio Processing RAS#ProcessorLA(17:0)DRAM InterfaceDA(8:0)InterfaceLD(7:0)HuffmanDBUS(15:1)LCS3#, LCS#(1:0)RISCDecoderDOU#DRAMLWR#Processor2Kx32 ROMDWE#LOE#2x32 SRAMCAS#ACLKAUX(7:1)AUXSerialATCLKMPEGAudioAINSeria
9、l AudioProcessorInterfaceAOUTInterfaceARFS64x32 ROMYUV(7:0)ATFS32x32 SRAMPCLK2XScreenARCLKRegistersVideo OutputPCLK VSYNCHSYNCTDMSEL-PLL(1:0)TDMInterfaceTDMCLKInterfaceOn ScreenTDMDRDisplayCPUCLKMiscTDMFSDRAM DMARESET#ControllerPort No.Port NameI/OFunction1,31,51VCC3-Supply voltage for 3.3V.2RAS#ODR
10、AM row address strobe (active low).3DWE#ODRAM write enable (active low).412MA(08)ODRAM multiplexed row and column address bus.1328DBUS(015)I/ODRAM data bus.29RESET#ISystem reset (active low).30,50,80,100GND-Ground.3239YUV(07)OY is luminance, UV are chrominance data bus for screen video interface.YUV
11、(07) for 8 bit YUV mode.40VSYNCI/OVertical sync for screen video interface, programmable for rising orfalling edge.41HSYNCI/OHorizontal sync for screen video interface, programmable for rising orfalling edge.42CPUCLKIRISC and system clock input.43PCLK2XI/OPixel clock: two times the actual pixel cloc
12、k for screen video interface.44PCLK I/OPixel clock qualifier in for screen video interface.4549,52,53,54AUX(07)I/OAuxiliary control pins (AUX0 and AUX1are open collectors).5562LD(07)I/ORISC interface data bus.63LWR#OUnused.64LOE#ORISC interface output enable (active low).65,66,67LCS(3,1,0)#ORISC int
13、erface chip select (active low).6879,8287LA(017)ORISC interface address bus.81VCC-Digital supply voltage for 5.0V.88ACLKI/OMaster clock for external audio DAC(8.192MHz, 11.2896MHz, 12.288MHz,16.9344MHz, and 18.432MHz).ODual-purpose pin. AOUT is the audio interface serial data output.Pins SEL -PLL(1:
14、 0) select phase-lock loop(PLL) clock frequency 89AOUT/SEL/PLL0ICPUCLK for the Visba : 00 = bypass PLL 01 = 54MHz PLL10 = 67.5MHz PLL 11 = 81MHz PLL90ATCLKI/OAudio transmit bit clock.ODual-purpose pin. ATFS is the audio interface transmit frame sync.91ATFS/SEL/PLL1IPins SEL -PLL(1: 0) select phase-l
15、ock loop(PLL) clock frequency CPUCLKfor the Visba. See the SEL -PLL0 pin above for the settings.92DOEODual-purpose pin. DRAM output enable (active low)/DRAM multiplexedrow and column address bus.93AINIAudio interface serial data input.94ARCLKIAudio receive bit clock.95ARFSIAudio interface receive fr
16、ame sync.96TDMCLKITDM interface serial clock.97TDMDRITDM interface serial data receive.98TDMFSITDM interface frame sync.99CAS#ODRAM column address strobe bank 0 (active low).Port Function of MPEG1 Video/Audio Processing : ES3880 (ICM2)RXD-V252/V252-H5CIRCUIT DESCRIPTIONPort No.Port NameI/OFunction1,
17、25,26,31,7275,77,91,100VSSIGround.5,16,32,6673, 78,90VCCISupply voltage for 5.0v.6DSC CIClock for programming to access internal registers.7AUX0I/OUnused.9AUX1I/OServo reverse or control pin.11AUX2I/OServo LD ON or control pin.70AUX3I/OUnused.69AUX4I/OServo CCW/Close or control pin.68AUX5I/OUnused.6
18、7AUX6I/OServo XLAT or control pin/VFD DO.14AUX7I/OServo BRKM/Sense or control pin/VFD DI.18AUX8I/OServo Mute/Open or control pin/VFD CLK.20AUX9I/OServo SQS0 or control pin.34AUX10I/OUnused.35AUX11I/OUnused.36AUX12I/OUnused.38AUX13I/OSerial interrupt/CD Mute or control pin.39AUX14I/OUnused.40AUX15I/O
19、Unused.8,81,83,8593,95,97,99DSC D(70)I/OData for programming to access internal registers.10DSC SIStrobe for programming to access internal registers.12DCLKODual purpose pin. DCLK is the MPEG decoder clock.EXT CLKIEXT CLK is the external clock EXT CLK is an input during bypass PLL mode.13RESET BIVid
20、eo reset (active low).15MUTEOAudio mute.17MCLKIAudio master clock.19TWSIDual purpose pin. TWS is the transmit audio frame sync.SPLL OUTOSPLL OUT is the select PLL output.21TSDITransmit audio data input.22TBCKITransmit audio bit clock.ODual purpose pin. RWS is the receive audio frame sync.Pins SEL PL
21、L (1,0) select the PLL clock frequency for the DCLK output.23RWSSEL PLL1 SEL PLL0 DCLKSEL PLL1I00 Bypass PLL (input mode)0 1 27MHz (output mode)1 0 32.4MHz (output mode)1 1 40.5MHz (output mode)24RSTOUT BOReset output (active low).24,273076NC-Unused.RSDODual purpose pin. RSD is the receive audio dat
22、a input.33SEL PLL0ISEL PLL0 along with SEL PLL1 select the PLL clock frequency for the DCLK output.37RBCKODual purpose pin. RBCK is the receive audio bit clock.SER INISER IN is the serial input DSC mode.41,51AGNDIAudio analog ground.42VCMIADC common mode reference (CMR) buffer output.43VREFPIDAC and
23、 ADC maximum reference.44VCCAAIAnalog VCC(5V).45,46AOR+, AOR-ORight channel output.47,48AOL-, AOL+OLeft channel output.49MIC1IMicrophone input 1.50MIC2IMicrophone input 2.Port Function of DAC & TV Encoder : ES3889 (ICM3)RXD-V252/V252-H6CIRCUIT DESCRIPTIONPort No.Port NameI/OFunction52VREF IInternal
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