Denon-TU1800DAB-tun-sm维修电路原理图.pdf
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1、SERVICE MANUALAM-FM STEREO/DAB TUNERMODELTU-1800DABFor U.K. modelTOKYO JAPANX0237 V.01 DE/CDM 0507Some illustrations using in this service manual areslightly different from the actual set.Please use this service manual with referring to theoperating instructions without fail.For purposes of improvem
2、ent, specifications anddesign are subject to change without notice.本文中使用、説明都合上現物多少異場合。修理際、必取扱説明書参照上、作業行。前、必読。本機、火災、感電、対安全性確保、配慮、法的電気用品安全法、所定許可得製造。従際、安全性維持、記載注意事項必守。本機仕様性能改良、予告変更。補修用性能部品保有期間、製造打切後8年。注意Denon Brand Company, D&M Holdings Inc.Ver. 1RadioFans.CN 收音机爱 好者资料库2TU-1800DABSAFETY PRECAUTIONSThe
3、following check should be performed for the continued protection of the customer and service technician.LEAKAGE CURRENT CHECKBefore returning the unit to the customer, make sure you make either (1) a leakage current check or (2) a line to chassisresistance check. If the leakage current exceeds 0.5 m
4、illiamps, or if the resistance from chassis to either side of thepower cord is less than 460 kohms, the unit is defective.注意注意事項守!特注意必要個所、部品、捺印、注意事項表示。注意書取扱説明書注意事項必守。感電注意!(1) 、交流電圧印加、通電時内部金属部触感電。従通電時、絶縁使用手袋着用、部品交換、電源抜、感電注意。(2) 内部、高電圧部分、通電時取扱、十分注意。指定部品使用!部品難燃性耐電圧安全上特性持。従交換部品、使用同特性部品使用。特配線図、部品表印指定安全上重
5、要部品必指定使用。部品取付配線引、元!安全上、絶縁材料使用、基板浮取付部品。内部配線引発熱部品高圧部品接近配慮、必元。後安全点検!取外、部品、配線元、個所周辺劣化点検、外部金属端子部、電源刃間絶縁、安全性確保確認。、点検時次注意願。注意安全上重要部品(絶縁方法)電源電源抜、外、電源入。 500絶縁抵抗計用、電源端子、外部露出金属部端子、端子、端子、入力端子間、絶縁抵抗値1以上、値以下、点検修理必要。本機使用多電気部品、機構部品安全上、特別特性持。特性場合、外観判別、部品高定格(定格電力、耐圧)持使用安全性維持、限。安全上特性持部品、配線図、部品表表示、必指定部品番号使用願。(1)配線図 (2)
6、部品表 表示。表示。指定部品異使用場合、感電、火災危険生恐。注意安全上重要部品RadioFans.CN 收音机爱 好者资料库3TU-1800DABLEVEL DIAGRAMS4TU-1800DAB BLOCK DIAGRAMS5TU-1800DABSEMICONDUCTORSOnly major semiconductors are shown, general semiconductors etc. are omitted to list.主半導体記載。汎用半導体記載省略。 1. ICsMB90F352C (IC300) 6TU-1800DABMB90F352C Terminal Funct
7、ionPin No.Pin NameI/OFunction1AvssVss2AVRHVcc3P62/AN2/PPG4(5)Ikey14P63/AN3/PPG6(7)Ikey25P64/AN4/PPG8(9)Iencoder_a6P65/AN5/PPGA(B)Iencoder_b7P66/AN6/PPGC(D)OFLT_RESET8P67/AN7/PPGE(F)OFLT_SELECT9P50/AN8/SIN2OFLT_CLOCK10P51/AN9/SOT2OFLT_DATA11P52/AN10/SCK2ORDI_SELECT12P53/AN11/TIN3O13P54/AN12/TOT3OLED_
8、STANDBY14P55/AN13OLED_STEREO15P56/AN14OLED_SECONDARY16P42/IN6/RX1/INT9ROLED_TUNED17P43/INT7/TX1OLED_RDS18VssGND19P40/X0A20P41/X1A21MD2MICOM UPGRADE22MD1MICOM UPGRADE23MD0MICOM UPGRADE24P00/AD00/INT8ODAB_I2C_CLOCK25P01/AD01/INT9ODAB_I2C_DATA26P02/AD02/INT10IAK4103_DATA_IN27P03/AD03/INT11OAK4103_CLOCK
9、28P04/AD04/INT12OAK4103_DATA_OUT29P05/AD05/INT13OAK4103_SELECT30P06/AD06/INT14IPOWER_DOWN31P07/AD07/INT15IREMOCON32P10/AD08/TIN1OPOWER_RELAY33P11/AD09/TOT1OMAIN_MUTE34P12/AD10/SIN3/INT11ROUPGRADE_RX35P13/AD1A/SOT3OUPGRADE_TX36P14/AD12/SCK3OPOWER_DAB37P15/AD13O38P16/AD14OEEPROM_DATA39P17/AD15OEEPROM_
10、CLOCK40P20/A16/PPG9(8)ODIT_RESET41P21/A17/PPGB(A)OFUNCTION_RELAY42P22/A18/PPGD?ODAC_RESET43P23/A19/PPGF(E)IDAC_MUTE_DETECT_R44P24/A20/IN0IDAC_MUTE_DETECT_L45RST46X14MHz47X04MHz48Vss49Vcc50C0.1UF/CERAMIC51P25/A21/IN1/ADTGODAC_MUTE52P44/FRCK0O53P45/FRCK1O54P30/ALE/IN4ODAB_ON55P31/RD/IN5IRDS_DATA56P32/
11、WRL/WR/INT10RIRDS_CLOCK57P33/WRHOPLL_CE58P34/HRQ/OUT4OPLL_DATA_OUT(PLL DATA TRANS )59P35/HAK/OUT5OPLL_CLOCK60P36/RDY/OUT6IPLL_DATA_IN(IF READ)61P37/CLK/OUT7OTUNER_MUTE62P60/AN0ITUNER_STEREO63P61/AN1ITUNER_TUNED64AvccVCC7TU-1800DABAK4103A (IC304) AK4103A BLOCK DIAGRAM654321V1TRANSMCLKPDNSDTIBICKLRCK7
12、FS0/CSN8U1DIF2DIF1DIF0TXPTXNVSSVDDTopView109FS1/CDTIFS2/CCLKFS3/CDTO11C112CKS1CKS0BLSANS192021222324181715161413Host SerialInterfaceAudio SerialInterfaceBICKLRCKSDTITXPMUXCRCC GeneratorPrescalerRS422 Line DriverBiphaseEncoderDIF2DIF1DIF0CKS1CKS0MCLKBLSTRANSVSSVDDTXNC1U1V1FS0FS1FS2FS3RegisterCSNCCLKC
13、DTICDTOANSPDN8TU-1800DABAK4103A TERMINAL FUNCTIONNo.Pin NameI/ODescription1V1IValidity Bit Input Pin2TRANSIAudio Routing Mode (Transparent Mode) Pin at Synchronous mode0: Normal mode, 1: Audio routing mode (transparent mode)3PDNIPower Down & Reset Pin(Pull-up Pin)When “L”, the AK4103A is powered-dow
14、n, TXP/N pins are “L” and thecontrol registers are reset to default values.4MCLKIMaster Clock Input Pin5SDTIIAudio Serial Data Input Pin6BICKI/OAudio Serial Data Clock Input/Output PinSerial Clock for SDTI pin which can be configured as an output based onthe DIF2-0 inputs.7LRCKI/OInput/Output Channe
15、l Clock PinIndicates left or right channel, and can be configured as an output based onthe DIF2-0 inputs.FS0ISampling Frequency Select 0 Pin at Synchronous mode (Pull-down Pin)CSNIHost Interface Chip Select Pin at Asynchronous mode (Pull-down Pin)8AKMODEIAK4112B Mode Pin at Audio routing mode(Pull-d
16、own Pin)0: Non-AKM receivers mode, 1: AK4112B modeFS1ISampling Frequency Select 1 Pin at Synchronous mode (Pull-down Pin)9CDTIIHost Interface Data Input Pin at Asynchronous mode(Pull-down Pin)FS2ISampling Frequency Select 2 Pin at Synchronous mode (Pull-down Pin)10CCLKIHost Interface Bit Clock Input
17、 Pin at Asynchronous mode (Pull-down Pin)FS3ISampling Frequency Select 3 Pin at Synchronous mode (Pull-down Pin)11CDTOOHost Interface Data Output Pin at Asynchronous mode (Pull-down Pin)12C1IChannel Status Bit Input Pin13ANSIAsynchronous/Synchronous Mode Select Pin(Pull-up Pin)0: Asynchronous mode,
18、1: Synchronous mode14BLSI/OBlock Start Input/Output Pin(Pull-down Pin)In normal mode, the channel status block output is “H” for the first fourbytes. In audio routing mode, the pin is configured as an input. When PDNpin = “L”, BLS pin goes “H” at Normal mode.15CKS0IClock Mode Select 0 Pin(Pull-up Pi
19、n)16CKS1IClock Mode Select 1 Pin(Pull-down Pin)17VDD-Power Supply Pin, 4.75V5.25V18VSS-Ground Pin, 0V19TXNONegative Differential Output Pin20TXPOPositive Differential Output Pin21DIF0IAudio Serial Interface Select 0 Pin(Pull-down Pin)22DIF1IAudio Serial Interface Select 1 Pin(Pull-down Pin)23DIF2IAu
20、dio Serial Interface Select 2 Pin(Pull-down Pin)24U1IUser Data Bit Input Pin for Channel 1(Pull-down Pin)Notes:1. Internal pull-up and pull-down resistors are connected on-chip. The value of the resistors is 43k (typ).2. All input pins except internal pull-down/pull-up pins should not be left floati
21、ng.9TU-1800DABBU1924F (IC306) 560pCMPVSS3comparator8th Switchedcapacitor filteranti-aliasingfilter100k120k100k270pMUXVref2.2 FVDD11AnalogPower supplyVSS11VDD22DigitalPower supplyVSS2XIXO4.332MHZ33pF333pF3PLL57kHZRDS/ARIPLL1187.5HzBi-phasedecoderMeasurementcircuitDifferentialdecoderT1T2RDATAQUALRCLK1
22、: VDD1and VDD2are separated within the IC.2: Have VDD2(digital power supply) of a sufficiently low impedance.3: Match the capacitor constants with the crystal manufacturer.12345678910111213141516RCLK(N.C.)XOXIVDD2VSS2T1T2QUALRDATAVrefMUXVDD1VSS1VSS3CMPReferenceclock(4)(3)(5)(6)(12)(11)(13)(14)(10)(7
23、)(8)(16)(2)(9)(1)10TU-1800DABM24C32 (IC704) BLOCK DIAGRAM SP8K5TB (IC105) SDAVSSSCLWCE1E0VCCE212348765WCE1E0Control LogicHigh VoltageGeneratorI/O Shift RegisterAddress Registerand CounterDataRegister1 PageX DecoderY DecoderSCLSDAE2(1) Tr1 Source(2) Tr1 Gate(3) Tr2 Source(4) Tr2 Gate(5) Tr2 Drain(6)
24、Tr2 Drain(7) Tr1 Drain(8) Tr1 Drain1 ESD PROTECTION DIODE2 BODY DIODE(1)(2) (3) (4)(8) (7) (6) (5)21(8)(7)(1)(2)21(6)(5)(3)(4)11TU-1800DABAD1852JRS (IC102) TERMINAL FUNCTION TOP VIEW(Not to Scale)28272625242322212019181716151234567891011121314AD1852FILTROUTROUTR+AGND96/48DEEMPZERORDGNDMCLKCLATCHCCLK
25、192/48NCCDATAAGNDOUTLOUTL+AVDDFILTBIDPM1IDPM0DVDDSDATABCLKLRCLKZEROLMUTERESETPinInput/OutputPin NameDescription1IDGNDDigital Ground.2IMCLKMaster Clock Input. Connect to an external clock source at either 256 FS, 384 FS,512 FS, 768 FS, or 1024 FS.3ICLATCHLatch Input for Control Data. This input is ri
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