Kenwood-XDV252-cs-sm 维修电路原理图.pdf
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1、MINI HiFi COMPONENT SYSTEMRXD-V252/V252-HSERVICE MANUAL 2001-10 PRINTED IN KOREAB51-5759-00 (K/K) 404 * Refer to parts list on page 27. In compliance with Federal Regulations, following are repro-duction of labels on, or inside the product relating to laserproduct safety.KENWOOD-Corp. certifies this
2、 equipment conforms to DHHSRegulations No.21 CFR 1040. 10, Chapter 1, subchapter J.DANGER : Laser radiation when open and interlock defeated. AVOID DIRECT EXPOSURE TO BEAM.*Refer to page 2 if you want to know system configuration.(XD-V252)*70%Dress ring (A21-3966-08)FRT cab assy *(A60-)FL panel *(B1
3、0-)Panel(VCD)(A60-2220-08)Knob(VOLUME)(K29-8047-08)Cassette lid(R)(A21-3959-08)Phone jack (E11-0942-08)Cassette lid(L) (A21-3958-08)Jack(MIC) (E11-0953-08)RadioFans.CN 收音机爱 好者资料库RXD-V252/V252-H2CONTENTS / ACCESSORIES / CAUTIONSCONTENTS / ACCESSORIES / CAUTIONS. 2EXTERNAL VIEW.3CIRCUIT DESCRIPTION.4A
4、DJUSTMENT.7WIRING DIAGRAM.8PC BOARD . 9SCHEMATIC DIAGRAM . 15EXPLODED VIEW .25PARTS LIST.27SPECIFICATIONS .Back coverContentsAC Plug Adaptor (1)(E03-0115-05) Use to adapt the plug on thepower cord to the shape of thewall outlet.(Accessory only for regions whereuse is necessary.) AM Loop Antenna(1)(T
5、90-0879-08)AA size battery(2)(UM/SUM-3, R6, HP-7 or similar) Remote Control(1)(A70-1574-08)FM Antenna(1)(T90-0883-08)Video Cable(1)(E30-7255-08)The marking of products using lasers(Except for some areas)The marking is located on the rear panel andsays this product has been classified as Class1. It m
6、eans that there is no danger of hazard-ous radiation outside the productCLASS 1LASER PRODUCTAccessoriesModelColorM(General Market)I(Malaysia)RXD-V252Blue-IRXD-V252-HGrayMI2System ConfigurationsCautionsAttentionPlease contact our KENWOOD Service Department in your side if you want the service informa
7、tion; Circuit Description. FullDescribed Parts list and so. Information is available to you by internet from us.RESETTING THE MICROCOMPUTERReset the microcomputer under the following con-ditions :To erase all of the stored memory contents (clockand timer settings, and tuner and CD presets).If the di
8、splay is not correct.If the operation is not correct.1Press the ON/STANDBY button to enterthe standby mode.2Whilst pressing down the 7 STOP button andthe SOUND MODE button, hold down theON/STANDBY button for at least 1 second.“CLEAR AL” will appear .Caution :The operation explained above will erase
9、all datastored in memory including clock and timer set-tings, and tuner and CD presets.TRANSPORTING THE UNITBefore you move this product to a new location,proceed as follows :1Press the ON/STANDBY button to turn thepower on.2Press the CD button.3Press the 0 OPEN/CLOSE button to open thedisc tray.Rem
10、ove all CDs inserted in the unit.4Press the 0 OPEN/CLOSE button to close thedisc tray.Make sure that “NO DISC” is displayed.5Press the ON/STANDBY button to enterthe standby mode and then unplug the AC powercord from the AC socket.SOUNDMODE ON/STANDBY7 STOP ON/STANDBYCD0 OPEN/CLOSERadioFans.CN 收音机爱 好
11、者资料库RXD-V252/V252-H3EXTERNAL VIEW* Refer to parts list on page 27. ANTENNAAM LOOPFM75 VIDEO/AUXVIDEOOUTSPAN SELECTOR230V240VFM 50kHz AM 9kHz FM 100kHz AM 10kHz +-LSPEAKERSRATED SPEAKER IMPEDANCE:6 OHMS MIN.RLRCabinet(TOP) (A02-3014-08)AC power cord (E30-2881-08)RCA socket(E02-0021-08)Lock terminal b
12、oard(E70-0151-08)FM Antenna (E70-0145-08)Slide switch(S62-0086-08)RCA socket(E63-1219-08)AC power cord bushing (J42-0338-08)RXD-V252/V252-H4CIRCUIT DESCRIPTIONBlock Diagram for MPEG1 Video/Audio Processing RAS#ProcessorLA(17:0) DRAM InterfaceDA(8:0)InterfaceLD(7:0)HuffmanDBUS(15:1)LCS3#, LCS#(1:0)RI
13、SCDecoderDOU#DRAMLWR#Processor 2Kx32 ROMDWE#LOE# 2x32 SRAMCAS#ACLKAUX(7:1)AUXSerialATCLKMPEGAudioAINSerial AudioProcessorInterfaceAOUTInterfaceARFS64x32 ROMYUV(7:0)ATFS32x32 SRAMPCLK2XScreenARCLKRegistersVideo OutputPCLK VSYNCHSYNCTDMSEL-PLL(1:0)TDMInterfaceTDMCLKInterface On ScreenTDMDR DisplayCPUC
14、LKMiscTDMFSDRAM DMARESET#ControllerPort No.Port NameI/OFunction1,31,51VCC3-Supply voltage for 3.3V.2RAS#ODRAM row address strobe (active low).3DWE#ODRAM write enable (active low).412MA(08)ODRAM multiplexed row and column address bus.1328DBUS(015)I/ODRAM data bus.29RESET#ISystem reset (active low).30
15、,50,80,100GND-Ground.3239YUV(07)OY is luminance, UV are chrominance data bus for screen video interface.YUV(07) for 8 bit YUV mode.40VSYNCI/OVertical sync for screen video interface, programmable for rising orfalling edge.41HSYNCI/OHorizontal sync for screen video interface, programmable for rising
16、orfalling edge.42CPUCLKIRISC and system clock input.43PCLK2XI/OPixel clock: two times the actual pixel clock for screen video interface.44PCLK I/OPixel clock qualifier in for screen video interface.4549,52,53,54AUX(07)I/OAuxiliary control pins (AUX0 and AUX1are open collectors).5562LD(07)I/ORISC int
17、erface data bus.63LWR#OUnused.64LOE#ORISC interface output enable (active low).65,66,67LCS(3,1,0)#ORISC interface chip select (active low).6879,8287LA(017)ORISC interface address bus.81VCC-Digital supply voltage for 5.0V.88ACLKI/OMaster clock for external audio DAC(8.192MHz, 11.2896MHz, 12.288MHz,16
18、.9344MHz, and 18.432MHz).ODual-purpose pin. AOUT is the audio interface serial data output.Pins SEL -PLL(1: 0) select phase-lock loop(PLL) clock frequency 89AOUT/SEL/PLL0ICPUCLK for the Visba : 00 = bypass PLL 01 = 54MHz PLL10 = 67.5MHz PLL 11 = 81MHz PLL90ATCLKI/OAudio transmit bit clock.ODual-purp
19、ose pin. ATFS is the audio interface transmit frame sync.91ATFS/SEL/PLL1IPins SEL -PLL(1: 0) select phase-lock loop(PLL) clock frequency CPUCLKfor the Visba. See the SEL -PLL0 pin above for the settings.92DOEODual-purpose pin. DRAM output enable (active low)/DRAM multiplexedrow and column address bu
20、s.93AINIAudio interface serial data input.94ARCLKIAudio receive bit clock.95ARFSIAudio interface receive frame sync.96TDMCLKITDM interface serial clock.97TDMDRITDM interface serial data receive.98TDMFSITDM interface frame sync.99CAS#ODRAM column address strobe bank 0 (active low).Port Function of MP
21、EG1 Video/Audio Processing : ES3880 (ICM2)RXD-V252/V252-H5CIRCUIT DESCRIPTIONPort No.Port NameI/OFunction1,25,26,31,7275,77,91,100VSSIGround.5,16,32,6673, 78,90VCCISupply voltage for 5.0v.6DSC CIClock for programming to access internal registers.7AUX0I/OUnused.9AUX1I/OServo reverse or control pin.11
22、AUX2I/OServo LD ON or control pin.70AUX3I/OUnused.69AUX4I/OServo CCW/Close or control pin.68AUX5I/OUnused.67AUX6I/OServo XLAT or control pin/VFD DO.14AUX7I/OServo BRKM/Sense or control pin/VFD DI.18AUX8I/OServo Mute/Open or control pin/VFD CLK.20AUX9I/OServo SQS0 or control pin.34AUX10I/OUnused.35AU
23、X11I/OUnused.36AUX12I/OUnused.38AUX13I/OSerial interrupt/CD Mute or control pin.39AUX14I/OUnused.40AUX15I/OUnused.8,81,83,8593,95,97,99DSC D(70)I/OData for programming to access internal registers.10DSC SIStrobe for programming to access internal registers.12DCLKODual purpose pin. DCLK is the MPEG d
24、ecoder clock.EXT CLKIEXT CLK is the external clock EXT CLK is an input during bypass PLL mode.13RESET BIVideo reset (active low).15MUTEOAudio mute.17MCLKIAudio master clock.19TWSIDual purpose pin. TWS is the transmit audio frame sync.SPLL OUTOSPLL OUT is the select PLL output.21TSDITransmit audio da
25、ta input.22TBCKITransmit audio bit clock.ODual purpose pin. RWS is the receive audio frame sync.Pins SEL PLL (1,0) select the PLL clock frequency for the DCLK output.23RWSSEL PLL1 SEL PLL0 DCLKSEL PLL1I0 0 Bypass PLL (input mode)0 1 27MHz (output mode)1 0 32.4MHz (output mode)1 1 40.5MHz (output mod
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