Arcam-DV78-dvd-sm维修电路原理图.pdf

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1、DiVAServiceManualDV78 DVD PlayerIssue 1.0ARCAMARCAMBringing music & movies to lifeBringing music & movies to lifeRadioFans.CN 收音机爱 好者资料库 Circuit Description Power Supply L959AY ! CCT diagram ! Component layout diagram ! Parts list Main Board L960AY ! CCT diagram ! Component layout diagram ! Parts li

2、st Display Board L961AY ! CCT diagram ! Component layout diagram ! Parts list Transformers ! L924TX ! L925TX Mechanical Assembly ! Exploded view diagram ! Mechanical and packing part list DV78 Contents List RadioFans.CN 收音机爱 好者资料库 Overview The DiVa DV78 is a completely new design platform that share

3、 a similar circuit topology to the earlier released Vaddis V based players such as the Diva 88+, Diva 89, DV27. The player is based around acclaimed Zoran Vaddis V chipset coupled to high specification Wolfson D to A converters for Left and Right channels. Power supply board. Non-switching Mains pow

4、er arrives at IEC inlet socket SKT1 and is filtered by EMC choke LI and Y caps C3 and C4, mains switch SW2a/b switches both Negative and Live phases before the power reaches the mains select switch at location SW1 the switch allows the primary windings of the transformer TX1 to be wired in either Pa

5、rallel or Series configuration. The Bridge rectifying Diode package at location D1 forms the basis of the conventional power stage and supplies a VN35V6 (-35.6v) to the Switch mode stage, transistor TR1 is biased by 2v7 Zener diode DZ1 and allows for the series Zener diodes DZ2, DZ3, DZ3 to supply t

6、he VN13V5 and VN19V rails. We will also see a simple A.C present circuit this is used for delayed output relay operation and fast relay closure under interrupted supply conditions thus preventing op-amp offsets from reaching the Audio output sockets. Switch mode The switch mode supply is formed arou

7、nd the Driver/Control chip IC1 UC3843 (used in regulating mode). The chip is referenced the 36.5V supply line and the Digital ground DGND, the supply for the chip is formed by the 12v Zener at location DZ6 and can be seen on Pin 7 as VCC. The power supply allows for the switch-mode to be tied the to

8、 Audio sampling frequency for any given compatible format. Fig 1 PSU clock control Fs Frequency select PSUFS1 Pin 11 IC305a PSUFS0 Pin 12 IC305a PSUCLK Output Pin 5 of IC305a 44.1 kHz 0 0 44.1 kHz 48 kHz 0 0 48 kHz 88.2 kHz 0 1 44.1kHz 96 kHz 0 1 48 kHz 176.4 kHz 1 0 44.1 kHz 192 kHz 1 0 48 kHz Othe

9、rs 1 1 OFF The PSU sync signal is driven into the power supply via Resistor R9 if no Sync is present the unit is set to free run x due to the RT/RC network attached to Pin 4. IC1 is running in regulated mode and monitors the voltage output on the +5V and +3V3 D.C lines, the two voltages are summed b

10、y TR8 and Driven into the VFB and Comp inputs of IC1, the Voltage is then regulated by changing the time base of the PWM output at pin 6 (longer the time base the lower the voltage), the PWM switching frequency is driven into the switch-mode transformer by the high speed Nmos device at position M1,

11、R5 is used to sense the Current across the gate of the Nmosfet and in the event of a short circuit will safely shut the power supply down. We derive the 12v Mech supply from the output of M1 using the Ultra-fast Diode at location D8 to rectify the PWM line. The D.C outputs from the switch mode have

12、extensive switch mode noise removing filters these are seen as 100n caps down to ground and Wire wound inductors in series with the supply rail. Power supply main board All the power supply rails are supplied to the main board via the 32 way FFC connector at location CON1001. The Digital supplies fr

13、om the switch mode stage of the power supply arrive as 3V3D, +5VD and +12VD we also see the Display board power supplies arrive as 19V, -9 and 13.5V all of the supplies have a second stage of implemented on the board to remove all traces of ultra-sonic noise. The 3V3D rail is the main 3V3 rail used

14、to power the digital circuitry; +5VD is used for all 5v Digital/Video supplies the +12VD is used for Scart switching. Diva Dv78 circuit description The 1V8 rail is derived from the 3V3 rail and is regulated by the adjustable regulator at location REG1003. The Analogue supply stages arrive at the mai

15、n board as +15V3 and 15V3 rails these are filtered L1002 and L1015 before being regulated by the adjustable regulators at locations REG1000 and REG1002 to provide +/- 12V rails for the Analogue output stage. Regulator REG1001 is fed from the +15V3 rail and forms the Audio DAC supply. The Display boa

16、rd requires several supply voltages these are simply passed through the main board, being filtered on the way to prevent transmission of noise through to the surrounding electronics. The display takes the +5V, -19V, -13V5 and -9V the 13V5 and 9V form a floating 4.5V supply biased relative to the 19V

17、 grid voltage. Display Board The main component of the Display board is IC1 this is a Vacuum Florescent Display driver with keyboard san and a serial data in/out interface. The Chip receives display drive serial data from the Vaddis V chip on the main board via Con1 on pins 12, 13 and 14 these will

18、be seen a DIN, STS and CLK this data is used to drive the VFD a DOUT line interfaces with the VADDIS V and supplies Keyboard Scan information. The keyboard scan is a 6 x 4 matrix with the Key Source appearing at S3, S4, S5, S6 and the Keyscan data returns appearing a K2, K3 and K4. Please see: above

19、 for power supply information. The Infra red pick-up at location RXI receives RC5 data and send the data to the Vaddis V on the main board via transistors TR2 and TR3, LED 2 is used to mix the rear panel RC5. The rear panel 3.5mm input jack receives modulated RC5 code; this is filtered for ultra son

20、ic noise by the inductors at locations L900 and L901 and then passed to the Infrared diode on the display at location LED2. Main Board electronics DV78. Zoran Vaddis V. The main processor/control chip on the main board is the Zoran Vaddis V at location IC202, this is the latest incarnation of the ve

21、ry popular Vaddis range of processors and allows for a much lower component count when compared to our earlier players as many of the playback functions have moved onto the Vaddis V silicon. Below you will see the major functions of the Vaddis V when used with the DV78. o Decoded Analogue Video outp

22、ut (internal DAC) used on the DV78 only. o SPDIF output. o Internal display interface. o Internal ATAPI interface. o Internal IR interface. o Serial in/out for RS232 (Optional). A more detailed explanation of the Vaddis V and peripheral components follows. Vaddis Power The Vaddis V is powered by two

23、 separate supplies the Vaddis requires a 1.8v supply for the core, this is regulated from the 3.3v rail by REG1003, the 3.3v rail is used to supply power to the I/P O/P ports of the chip. ATAPI interface CON203 is an ATAPI interface on a 40 way IDE connector. This is decoupled from the Drive via an

24、array of decoupling resistors as required by the ATAPI spec. Display Board interface The display board interface is on the 16 way FFC flexi foil connector at location CON202. Power for the display also travels on the connector. There are 4 wires to interface with the VFD driver chip these are seen a

25、s. o XFPDIN - Data to the display board o FPDOUT - Data from the display board o XFPCLK - Clock o XFPSEL - Chip select The above control lines are level shifted to 5v logic from 3.3v levels by IC200 (74HCT125) these are the levels required by the VFD drive chip. The IR output from the Display board

26、arrives as IRRCV this is an open collector signal, which can be wire-Ord with the re-panel remote input. Digital Audio The Digital audio leaves the chip as 1 data line labelled as. o ADAT0 - Left and Right channel data Along with the ADAT line we will also see the ABCLK and ALRCK as required for IS2

27、 data conversion. The Vaddis V also supplies a direct SPDIF output for interfacing with ancillary processing equipment. Flash/ SDRAM IC203 is a 64Mbit (32 bit x 2Meg) SDRAM. It runs at 135MHz IC205 is a 16Mbit (16 bit x 1Meg) intel type flash IC for program storage (Player software). The flash inter

28、faces to the Vaddis V using the SDRAM bus it may appear that the bus connects to the flash in a random manner, however this is simply because the Vaddis bus is multiplexed that way. The Flash will be accessed at power up and the contents are copied to the SDRAM the program will then be run from the

29、SDRAM. Series resistors are employed to isolate the flash bus from the main SDRAM bus. EEPROM IC204 is a 8kBit (1K x 8) Serial EEPROM. This is used for storage of non-volatile storage of player settings, region settings and bookmark data. Clocks CLK27MV is the 27Mhz clock for video. It is used to ge

30、nerate the 135Mhz clock for the Vaddis microprocessor and DSP. The MCLKV is the audio master clock for the Vaddis. We run the Vaddis in PLL bypass mode and generate or own master clock (see main clock section of manual) for higher accuracy and improved performance across Audio and Video. RESET IC201

31、 is a reset generator chip that monitors the +3.3V rail and ensures a reset signal PWR_ON_RESET* is generated on power up, or if the mains power dips below an operational level. This signal is used to reset the Vaddis V and Flash micro only. The Vaddis V line labelled as RESET* resets the remaining

32、circuitry of the player apart from the HDMI chip, this has its own reset line labelled as HDMI_RESET this is necessary if we require to reset the HDMI chip only (for example when the HDMI sink is connected and then disconnected). Serial Port The VADDIS V can interface with the external world via the

33、 RS232 connector at location CON900 and the RS232 Transceiver at location IC900, the serial data lines are shown as SERIAL RX and SERIAL TX these lines allow for direct control over the unit via RS232. Fig 2. GPIO control signals from the Vaddis V Single Name I/P-O/P Function PSUFSO-1 Output Control

34、 PSU Clock divider ENABLE_AV Output SCART control High in normal operation and low in standby 16/9 Output Scart 16/9 anamorphic control line GAIN_SCALING Output High for HDCD gain scaling ML_8740_0-2 Output SPI load signal for Audio DACs 0 MC Output SPI clock signal for DAC control MD Output SPI dat

35、a signal for DAC control FSELE0-1 Output Frequency select generator MUTE* Output Active low audio mute signal RESET* Output System reset Clocks and SPDIF stage. IC300 is a PLL1700E clock generator IC the chip is powered from the +5V(D) rail. The Chip runs in software mode and is slaved from the Vadd

36、is V (data coming in on the MD line). X300 is a 27Mhz crystal that IC300 uses to generate all the video and audio clocks required by the system the crystal sits on the XTI and XTO pins of the chip, the 27Mhz output at Pin 10 (MCKO) is used to drive the Vaddis chip directly bypassing the internal PLL

37、. The frequency of the audio master is dependent on the on the current audio sample rate (I.e the sample rate required by the format CD=44.1Khz and DVD=48khz etc) and this is set by the system micro via the MD, MC and ML_1700 lines from the Vaddis V. Clock Buffer IC301 us used to buffer the audio ma

38、ster clock. The circuit is arranged so that each device that requires the audio master clock has its own driver these are seen as. o MCLK_DAC0 - Pin 18 o MCLK_DAC1 Pin 16 o MCLK_DAC2 Pin 14 o MCLK_VADDIS Pin 3 o MCLK_HDMI Pin 9 We also run the Mute Line from the Vaddis V IC301 this can be seen on Pi

39、n 12 and drives transistor TR401, the transistor pulls the relays RLY400, RLY500, RLY600 to ground and un-mutes the audio outputs. IS2 Audio Data IC302 and IC309 are buffers for the 12S signals these ensure that the signals travelling to the DACs are point to point. IC302 deals with the ALRCK and AB

40、CLK and IC309(NF DV78) the ADAT0,1,2 all signal are split into three separate lines for the three stereo DACS. PSU Clock Divider IC304 a/b form a clock divide by 1, 2 or 4 to ensure the PSU clock is always either 44.1kHz or 48Khz (See fig 1 within the power supply description section). The circuit i

41、s fed from the ALRCLK (Audio clock) the selected PSUCLK is controlled by PSUFSO and PSUFS1. The output of the PSU circuit can be seen to leave IC305 on pin 5 via R311. Please see Fig 1 for PSU control information. The circuit will also switch the PSUCLK off when switching between sample rates (the P

42、SU will free run when the PSUCLK is not present). SPDIF Output The SPDIF output consists of IC901 implemented as a inline buffer and parallel output buffer. Gate A buffers the signal so that the SPDIF line from the VADDIS sees fewer loads and form a feed to the Optical output transmitter, gates B,C

43、and D drive the SPDIF in parallel so that we can drive a 75ohm load adequately. The resistors at the output of IC901 are arrange so that the output will be 500mV pk-pk when the output is terminated with a 75 ohm load at the same time the output impedance of the circuit is 75ohms as required by the S

44、ony Philips Digital Interface specification. Left and Right channel D to A stages The Wolfson WM8740 stereo DAC ay location IC403 requires +5V(A) and a +3V3 supply along with the Digital Audio data lines already described in this guide. The Left channel output only will be described in this section.

45、 IC400B and associated components form a 2nd order Bessel filter with a differential input and a gain of 1 this follow by a output buffer IC401B, the gain of IC401B is control by the switching chip at location IC402, in normal use the Gain of IC401B is set to 1.1 but in HDCD mode the IC402 switches

46、a second 10k resistor in parele with R413 and the gain is set to 2.2 allowing for the higher audio output required by the HDCD standard. C436 is an A.C coupling capacitor used to remove the few mV of offset that the DAC produces; D400 provides protection against from ESD. The all output relays are u

47、nder control of the Vaddis V chip but will also mute the outputs instantly under mains failure conditions. Switching drive is provided by TR401 (MUTE_BUF) and TR400 (AC_PRES) the relays are in mute mode if either the input to TR401 is Low or if the input to TR400 is high. Please note: The Scart left

48、/right audio is fed from the outputs of the left/right audio stages. Video Output stage The DV78 video output stage makes use of the VADDIS Vs on board video DAC stages and as such does not use the superior Analogue devices video encoder DV79/DV29 and is fed by the following video lines from the Vad

49、dis V. o Composite o SVID_C o SVID_Y o V or Red o U or Blue o Y or Green If we look at the Composite stage only, we will see that the Analogue video signal is filtered by C710, C711 and L705 before being passed through the Video Op-amp at location IC701 the output is decoupled by capacitor C738 befo

50、re reaching R714 this forms the 75 ohm load required. All other video outputs are identical. SCART Output RGB and Composite video signals as well as Left and right audio signals are all present on the SCART output socket. As the RGB and YUV signals share the same output port at the Vaddis V the play