PassLabs-Aleph0-pwr-sm 维修电路原理图.pdf

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1、Aleph 0s Service Manual Version 1.0 - 1.3PRODUCT DESCRIPTIONThe Aleph 0s is a high performance Mosfet single-ended Class A stereo audio poweramplifier, intended for maximum performance in reproduction of music. It is a simple design,having only three gain stages: input differential pair, cascoded vo

2、ltage gain stage, andoutput followers. All three gain stages are biased by constant current sources from thenegative supply. The output stage will operate as a single ended class A system at lowerpower levels and will operate as a push-pull class A system at levels above the bias point ofthe constan

3、t current source.SIMPLIFIED SCHEMATICTo best understand the operation of the amplifier, refer to the simplified schematic Figure 1.The front end of the amplifier accepts a balanced or unbalanced input signal at two Nchannel Mosfets operating as a differential pair. They are provided with bias by a c

4、urrentsource from the negative rail which operates at a constant 8 milliamps. The output of thedifferential pair drives a P channel Mosfet which provides voltage and current gain. At theoutput of this second stage you will see the full voltage swing of the amplifier.This second gain stage is provide

5、d with a single-ended Class A current bias from anothercurrent source from the negative supply which provides a constant 30 milliamps current.Between the current source and the drain of the P channel device is a constant voltagesource which is used to provide voltage bias to the output Mosfet transi

6、stors.The amplifier has complementary N and P channel output transistors operated as sourcefollowers, so that they provide only current gain. High current single ended Class A bias isprovided by yet another constant current source from the negative supply. This currentsource provides greater than 1

7、amp of constant current per channelCOMPLETE SCHEMATICFor purposes of clarity and simplicity, the complete schematic of the Aleph 0s is broken upinto the following sections: Power supply, Front end, and Output Stage.Figure 2 shows the power supply schematic. An IEC standard AC line connector connects

8、 tothe primary of a toroidal power transformer through an inrush suppression thermistor, fastblow fuse, a power switch, and a thermostat. Fig 2 shows the transformer wired for 120VAC, and the transformer can be adapted to 240 VAC by connecting the two primarywindings in series. 100 volt operation re

9、quires a special transformer.The secondary system consists of a bridge rectifier and four 31,000 uF capacitors. Thesecondary DC voltage is approximately plus and minus 40 volts. The front end circuitry ofthe amplifier is decoupled from the main supply by RC filters.Figure 3 shows one half of the out

10、put stage. Both halves run exactly in parallel.RadioFans.CN 收音机爱 好者资料库RadioFans.CN 收音机爱 好者资料库9.1VZ2029.1VZ201R201221221R202R207.33R208.33Q203IRF9240IRF244Q201221R204Q204MPSA42221R2031.3R206Q202IRF244GSDR20547.5K4.7C201PL10OS10.S01V+10/10/93PASSALEPH 0S OUTPUT STAGE (1/2)-DISD+DOUTV-ABCD4321DCBA1234o

11、fSheetDrawn byRevNumberTitleSizeADateFilenameFollowing are the front end circuits and PC board component placements for Revisionnumbers 1.0 through 1.3. All are very similar, and while the following description appliesspecifically to Rev 1.0, the comments apply to all versions.The circuit formed by

12、Q101, Z102, R108 and R107 is a constant current source designed tobias Z101, the voltage reference for the front end constant current sources, and Q7, thevoltage gain stage cascode transistor. This current source and reference circuit is commonto both channels. Further references are to each channel

13、 singly, with both channels havingidentical circuits and part references.Q3 and Q4 are constant current sources which bias the front end. They are driven by Z101at 9.1 volts, resulting in approximately 4.5 volts across their source resistors, R3 and R10,giving approximately 8 ma and 30 ma constant c

14、urrent.The input differential transistors Q1 and Q2 are power Mosfet transistors which have beenmatched to .01 volts threshold voltages at 4 milliamps current. The gates of these devicesare connected to differential networks formed by R5, 6, 13-18. These form a true differentialamplifier for balance

15、d input and can be operated unbalanced by simply driving the positiveinput (XLR pin 2) with or without shorting the negative input (XLR pin 3) to ground. Shortingthe negative input to ground provides twice the voltage gain over leaving it unterminated,but either method of operation is acceptable.Zen

16、er diodes Z1 and 2 protect the input transistors from outside transient voltages. Q1drives Q6 in common source mode which is in cascode (common gate) connection with Q7.At the same time, Q2 drives the source of Q7 in a folded cascode connection, so that bothinput transistors drive the secondary gain

17、 stage. The DC offset point of this system is set byP1.While the amplifier is primarily biased by the output stage constant current source, thedesign provides for pull operation beyond the constant current bias point with a set of Pchannel source followers. The bias relation between the P and N chan

18、nel source followeroutput devices is set by the constant voltage circuit of Q5 and adjusted by P2. Normally, theP channel output stage will be biased at about 10% of the value of the constant currentsource, or about 100 ma.C5 provides 10 picofarads of forward compensation in the feedback loop. C6 pr

19、ovides 39 pfof compensation for Q6.Z3 provides protection for the gate of Q7 when Q6 is shut down on a negative waveformclip. Q8 provides current limiting for Q6 during a positive waveform clip.R1 and C7 provide loading at radio frequencies. If R1 is damaged, it is a sure sign of highpower at high f

20、requencies, such as full power at 100 KHz or Square waves above 20 KHz.Unless it is on a test bench, the only way the amplifier will experience this will be in systemoscillation, where the output of the amplifier is allowed to bleed back to the input. This isgenerally due to wiring fault in the syst

21、em.4.7UFC8C3390PF2.7R1GNDC4390PF.047C7THERMISTORT150K9.1VZ3R17100K4.75KR16R112.2K5KP1CWWCCWIRFD210Q1IRFD210Q29.1VZ19.1VZ2680R10Q3IRF610221R9Z1019.1VR1094.75KZ1029.1VMPSA92Q101R1084.75KR10715KQ8MPSA92R7221221R8IRF9510Q7Q6IRFD92104.75R2IRFD210Q5Q4IRF610150R3R4221100KR18C510PF7.5KR12GND5KP2CWWCCWC639PF

22、C2390PFC1390PF221R64.75KR144.75KR15R134.75KR5221+DRIVEOUTPUT-DRIVE+ INPUT- INPUTALEPH 0S FRONT ENDPL10FE.S01PASSV-V+12/13/93ABCD4321DCBA1234BRevNumberTitleSizeDateFilenameDrawn byofSheet220 50VC10610R1033.3K 2WR1053.3K 2WR10410R102220 50VC1054.7UFC82.7R1GND.047C7THERMISTORT150K9.1VZ3R17100K4.75KR16R

23、113.3K5KP1CWWCCWIRFD210Q1IRFD210Q29.1VZ19.1VZ2680R10Q3IRF610221R9Z1019.1VR1094.75KZ1029.1VMPSA92Q101R1084.75KR10715KQ8MPSA92R7221221R8IRF9510Q7Q6IRFD921010R2IRFD210Q5Q4IRF610150R3R4221100KR18C510PF4.75KR12GND5KP2CWWCCWC639PFC2390PFC1390PF221R64.75KR144.75KR15R134.75KR5221FIG 3OTHER CHV-V+DRIVEOUTPUT

24、-DRIVE11/6/93+ INPUT- INPUTALEPH 0S FRONT ENDPASSPL10FE11.S01ABCD4321DCBA1234BRevNumberTitleSizeDateFilenameDrawn byofSheet221R54.75KR13R154.75KR144.75KR6221390PFC1390PFC239PFC6GNDR18100K221R4R3150IRF610Q4Q5IRFD210R210IRFD9210Q6Q7IRF9510R8221221R7MPSA92Q815KR1074.75KR108Q101MPSA929.1VZ1024.75KR1099.

25、1VZ101R9221IRF610Q3R10680Z29.1VZ19.1VQ2IRFD210Q1IRFD210P15KCCWWCW2.2KR11R164.75K100KR17Z39.1V150KT1THERMISTORC7.047GNDR12.7C84.7UFR?2.2KR?2.2KR?2.2K10PFC5R124.75KP25KCCWWCW680PFC3680PFC4V+V-PASSPL10FE.S01ALEPH 0S FRONT END- INPUT+ INPUT+11/6/93-DRIVEOUTPUT+DRIVEABCD4321DCBA1234BRevNumberTitleSizeDat

26、eFilenameDrawn byofSheet3.3K 2WR10510R1033.3K 2WR10410R102220 50VC101220 50VC10210R1910R209.1VZ19.1VZ29.1VZ5100KR7C4220 50V100KR89.1VZ49.1VZ3220 50VC35KP2CWWCCWC510PFR1333K 2WVALR14Z1029.1VR10115K 2W4.7UFC82.7 2WR11GND.047C7R5100K4.75KR4R93.3K5KP1CWWCCWIRFD210Q1IRFD210Q2680R17Q3IRF610221R15Z1019.1VQ

27、8MPSA92221R12IRF9510Q7Q6IRFD921010R10IRFD210Q5Q4IRF610150R18R16221100KR6C639PFC1390PFC2390PF4.75KR14.75KR3R24.75KC9.1 UF-V+V4/25/94+DRIVEOUTPUT-DRIVE+ INPUT- INPUTALEPH 0S FRONT ENDPASSPL10FE13.S01ABCD4321DCBA1234BRevNumberTitleSizeDateFilenameDrawn byofSheetFigure 3 shows the output stage schematic

28、. It shows one-half of one channels output stage,which contains 6 output devices. The top IRF244 is an output follower. The bottom IRF244Mosfet is a constant current source. The P channel IRF9240 transistor is a follower whichcontributes beyond the current provided by the constant current source.On

29、each module, R205 supplies current to Q204, which is the driver for the output stageactive current source. The gate of the output stage current source Mosfet is driven by thecollector of Q204 at about 4.5 volts. This voltage is controlled through current feedback fromthe source of the Mosfet connect

30、ed to the base of Q204. The Base-Emitter junction voltageof Q204 is about .7 volt, and the circuit operates to hold the source voltages about .7 voltabove the negative rail voltage, which puts .7 volt across the 1.3 ohm source resistor oneach current source Mosfet, which controls 580 ma each times 2

31、 modules, or 1.15 ampsconstant current biasing the output stage.Note that the output devices are matched for Gate to Source voltages at 200 ma on alltransistors to within .1 volt. This means that all IRF9240 devices within an amplifier arematched, and that all IRF244s used as output followers are ma

32、tched, and all IRF244s usedas constant current sources are matched. The match voltage of each transistor is written onthe case at Pass Labs, and ranges from 3.00 to 4.99. If it is necessary to replace devices inthe field, they must be a match. Devices with a particular number may be obtained fromPas

33、s Laboratories.Figure 5 shows the PC layout of the front end board. Note that the control and powerconnections to the output stage are through wires connected by screw-down terminalconnectors. The wires coming off the main board are attached to the output stage modulesby corresponding connections.AD

34、JUSTMENTS AND SERVICEInitial power up procedures: For an amplifier in unknown adjustment or being powered up forthe first time after repair or modification.Essential Equipment: Oscilloscope, Audio signal source, Variable AC power source, AC linecurrent meter, 8 ohm load.A distortion analyzer is very

35、 helpful confirming proper operation, but is not essential toadjustment of an otherwise working amplifier.If you do not have an AC line current meter, you may place a .1 ohm 5 watt power resistor inseries with the AC line (cold) and measure the voltage across it (1 amp = .1 volt AC), takingcare not

36、to electrocute yourself.Check the AC line fuseSet signal source to .1V at 1 KHzAttach signal sourceAttach 8 ohm load.Monitor the amplifier output with oscilloscope, Set the AC line source to 0.AC power switch onP1 (offset adjust) should be at mid-position.P2 (bias adjust) should be at mid-position.S

37、lowly turn up the AC line voltage to 1/3 while watching the current draw.Rated power draw: 1.4 A avg. 120 VAC, .7 A avg. 240 VACRated power draw: 1.4 A 120 V 1.4 (power factor) = 240 WattsYou will see the amplifier draw current near to rating when the AC line voltage is at 1/3rating or more. At 1/3

38、AC line voltage, adjust P2 for minimum current draw (maximumresistance for P2). At this position, the power draw of the amplifier will be that of the outputstage constant current source.Different means of measurement of AC current draw will give slightly different results.However the constant curren

39、t source of the output stage draws most of the power in theamplifier and is quite accurate. On a working amplifier it may be used as the basis or normfor current measurement.If the DC offset at the output is excessive, then you should adjust P1 on the front endboard. Initially this will usually be s

40、et to middle. P1 will have to be readjusted after awarm-up period of at least an hour.If the power draw is correct and a clean 2 volt signal appears at the output and DC offset isminimized, then the amplifier probably works. You may slowly increase the AC line voltageto full rating while watching th

41、e output wave form and the current draw.Then increase the signal level to full output of the amplifier, verifying proper operation upto clipping. With the bias set to minimum, there will be some distortion at higher powerlevels, which is expected.After you have verified that the amplifier will drive

42、 an 8 ohm load to 40 watts, you can set thebias point. It is quite easy. First, make note of the current draw of the amplifier with bothchannels at minimum bias and with the amplifier cold. Multiply this figure by 20%. Thenwithout a load or signal, idle the amplifier for an hour or more. Noting the

43、minimum currentdraw after warm-up, adjust P2 of one channel so that the current draw is one half thedifference between the warm value and 1.2 times the cold value. Then adjust P2 of the otherchannel so that the current draw is not 1.2 times the cold minimum draw.Typical example: The cold AC current

44、draw with the bias at minimum is 1.2 amps. Let theamplifier warm up for at least an hour. Now the bias will be 1.0 amps. Set the bias P2 of onechannel to one-half the difference between the 1.0 amps and 1.2 amps plus 20%, or 1.44amps. One half of the difference in this case is 1.22 amps, so set the

45、first channel for 1.22amp AC line draw. Now set the second channel so that the AC line draw is now 1.44 amps.At the factory, we set 120 volt units for 1.4 A average AC line draw, with 1.6 A for 100 voltline, and .7 A for 240 volt line. Your voltmeter might be different, which is why we have theabove

46、 procedure. When you are done, the warmed up amplifier should draw AC line currentwhich is 20% more than the minimum possible line draw with the amplifier cold.Any questions, call the factory.The DC offset must be readjusted after warm-up also, setting it as close to 0 DC aspossible. The DC offset w

47、ill drift for an hour after this, and must be set again.Probably the least precise performance parameter of the Aleph 0s is the DC offset at theoutput, and this relates to the single-ended nature of the design and the pure DC approachto the circuitry.On a warmed-up amplifier, the offset will general

48、ly be 50 mV or so, but it will show cold DCoffset of 300 mV or even more. The DC offset must be final adjusted after the amplifier hasbeen allowed to warm up for an hour (heat sink temperatures of 50 degrees C. or so). Thetop assembly of the amplifier must be closed up during operation.After adjusti

49、ng, check the DC offset at half hour intervals, readjusting if necessary. At thefactory we monitor the offset during a three day burn in, and we expect it to stay within 100mV with an ambient temperature between 70 and 80 degrees F. At higher ambienttemperatures the offset voltage will drift positiv

50、e, and at lower ambient temperatures it willdrift negative. It is permissible and preferred to adjust the offset against a known ambienttemperature.Notes on transistor matchingInput Mosfets (IRFD110 or IRFD210) must have their threshold voltages matched to about10 mV at 4 ma of current. This is acco