HarmanKardon-AVR2650-avr-sm3维修电路原理图.pdf

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1、256M Double Data Rate Synchronous DRAMA3S56D30FTPA3S56D40FTPPIN FUNCTIONCLK, /CLKInputClock: CLK and /CLK are differential clock inputs. All address and controlinput signals are sampled on the crossing of the positive edge of CLK andnegative edge of /CLK. Output (read) data is referenced to the cros

2、sings ofCLK and /CLK (both directions of crossing).CKEInputClock Enable: CKE controls Power Down and Self Refresh. Taking CKE LOW provides Precharge Power Down or Self Refresh (all banks idle),or Active Power Down (row active in any bank).Taking CKE HIGH provides Power Down exit or Self Refresh exit

3、.After Self Refresh is started, CKE becomes asynchronous input. Power Down and Self Refresh is maintained as long as CKE is LOW./CSInputChip Select: When /CS is HIGH, any command means No Operation./RAS, /CAS, /WEInputCombination of /RAS, /CAS, /WE defines basic commands.A0-12InputA0-12 specify the

4、Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-12. The Column Address is specified by A0-9(x8) and A0-8(x16). A10 is also used to indicate precharge option. When A10 is HIGH at a Read / Write command, an Auto Prechargeis performed. When A10 is HIGH at a Precharge

5、command, all banks are precharged. BA0,1InputDQ0-7 (x8),DQ0-15 (x16),Input / OutputDQS (x8)Vdd, VssPower SupplyPower Supply for the memory array and peripheral circuitry.VddQ, VssQPower SupplyVddQ and VssQ are supplied to DQ, DQS buffers.Bank Address: BA0,1 specifies one of four banks to which a com

6、mand is applied.BA0,1 must be set with Active, Precharge, Read, Write commands. Data Input/Output: Data busData Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-DQ7;

7、 UDQS correspond to the data on DQ8-DQ15SYMBOLTYPEDESCRIPTIONDM (x8)InputInput Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the

8、 DM loading matches the DQand DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7; UDM corresponds to the data on DQ8-DQ15.Input / OutputVREFInputSSTL_2 reference voltage.UDQS, LDQS (x16)UDM, LDM (x16)AVR 2650 AVR 2650 harman/kardonharman/kardon 121RadioFans.CN 收音机爱 好者资料库 12-Bit, 170 MH

9、z Video and Graphics Digitizer with 3D Comb Filter Decoder and Quad HDMI 1.4 Fast Switching Receiver PRELIMINARY ADV7844 FEATURES Quad HDMI 1.4 Fast Switching Receiver 170 MHz Video and Graphics Digitizer 3D Comb Filter Video Decoder SCART Fast Blank Support Adaptive HDMI Equaliser Integrated CEC Co

10、ntroller HDMI Repeater Support Advanced VBI data slicer Video and Graphics Digitizer Four 170 MHz, 12-bit ADCs, 12-channel analog input mux 525i-/625i-component analog input 525p-/625p-component progressive scan support 720p-/1080i-/1080p-component HDTV support Low refresh rates (24/25/30 Hz) suppor

11、t for 720p/1080p Digitizes RGB graphics up to 1600 1200 at 60 Hz (UXGA) 3D Video Decoder NTSC/PAL/SECAM color standards support NTSC/PAL 2D/3D motion detecting comb filter Advanced time-base correction (TBC) with frame synchronization Interlaced-to-progressive conversion for 525i and 625i IF compens

12、ation filters Vertical peaking and horizontal peaking filters Robust synchronization extraction for poor video source 4:1 HDMI 1.4 225 MHz Receiver Fast-Switching of HDMI ports 2:2 HEAC muxing support 2 HEAC channel support 2 Ethernet Interfaces for HEC Support SPDIF interface for ARC support. 3D Vi

13、deo format support including frame packing 1080p 24Hz, 720p 50 Hz, 720p 60Hz Full colorimetry support including sYCC601, Adobe RGB, Adobe YCC 601 36-/30-bit Deep Color and 24-bit color support HDCP 1.3 support with internal HDCP Keys +5V Detect and Hot plug assert for each HDMI port Full HDMI Audio

14、Support including HBR, DSD, DST Advanced Audio mute feature Flexible digital audio output interfaces Supports up to 5 SPDIF outputs, Supports up to 4 I2S outputs General Highly flexible 36-bit pixel output interface Internal EDID RAM for HDMI and graphics Dual STDI (standard identification) function

15、 support Any-to-any, 3 3 color space conversion (CSC) matrix 2 programmable interrupt request output pins Simultaneous analog processing and HDMI monitoring APPLICATIONS Advanced TVs PDP HDTVs LCD TVs (HDTV ready) LCD/DLP rear projection HDTVs CRT HDTVs LCoS HDTVs AVR video receivers LCD/DLP front p

16、rojectors HDTV STBs with PVR Projectors FUNCTIONAL BLOCK DIAGRAM 36-BIT YCbCr/RGBADV7844SCART RGB+ CVBSCVBSYCHDMI 4HDMI 3HDMI 2HDMI 1HD YPbPrINPUT MUXSD/PSYPbPrSDRAMSCART GSCART BSCART RCVBSCVBSSCARTCVBSI2S364Y/GPb/BPr/R48GRAPHICSRGBADCADCADCADCTO AUDIOPROCESSORTMDSDDCTMDSDDCTMDSDDCTMDSDDCDEEPCOLORH

17、DMI RxHDCPKEYSSPDIFDSDSDPCLKHS/VSFIELD/DECLKHS/VSFIELD/DECLKHS/VSFIELD/DECVBS 3D YCS-VIDEOSCARTCPYPbPr525p/625p720p/1080i1080p/UXGARGBOUTPUT MUXOUTPUT MUXHBRAUDIOOUTPUT5MCLKSCLKMCLKSCLKDATADATAFASTSWITCHSPDIFHEACETHERNET 1ETHERNET 2 Figure 1. AVR 2650 AVR 2650 harman/kardonharman/kardon 122RadioFans

18、.CN 收音机爱 好者资料库ADV7844 PRELIMINARY Rev. PrC| Page 4 of 35 DETAILED FUNCTIONAL BLOCK DIAGRAM ANALOG FRONT ENDCLAMPADC0LLC GENERATIONCONTROLCONTROLAND DATASYNC PROCESSINGAND CLOCK GENERATIONFILTERDDCA_SDA / DDCA_SCLYPrPbCVBSYCSCART RGBRGBAOUTCECAVLINK12CLAMPADC112CLAMPADC212CLAMPADC31212-CHANNELINPUTMA

19、TRIXHS/CS,VS/FIELDTRI1 TOTRI4SYNC1SYNC2HS_IN1VS_IN1HS_IN2/TRI5VS_IN2/TRI6TRI-LEVELSLICERSCLSDACONTROL INTERFACEI2CPLLRXA_CRXB_CRXC_CRXD_CRXA_0RXA_1RXA_2RXB_0RXB_1RXB_2RXC_0RXC_1RXC_2RXD_0RXD_1RXD_2AVLINKCONTROLLERCEC CONTROLLEREDID/REPEATERCONTROLLEREQUALIZERSAMPLEREQUALIZERSAMPLEREQUALIZERSAMPLEREQ

20、UALIZERSAMPLERHDCPBLOCKPACKETPROCESSORDIGITAL PROCESSING BLOCKCOMPONENT PROCESSORVIDEO DATA PROCESSORVIDEO OUTPUT FORMATTERINT1LLCP0 TO P11P12 TO P23P24 TO P35INT2STANDARD DEFINITION PROCESSOR (SDP)HS/CSVS/FIELDDESYNC_OUT121212MUXPACKET/INFOFRAMEMEMORY4:2:2 TO 4:4:4CONVERSIONAUDIOPROCESSOR2D COMB3D

21、COMBTBCMACROVISIONDETECTIONSTANDARDAUTODECTIONCTI and LTIVERTICALPEAKINGHORIZONTALPEAKINGFASTBLANKOVERLAYCONTROLDDR/SDR-SDRAM INTERFACEINTERLACETO PROGRESSIVECONVERSIONCOLOR SPACECONVERSIONANCILLARYDATAFORMATTERI2CREADBACKFAST I2CINTERFACEVSIDECODERACTIVE PEAKAND HSYNC DEPTHNOISE ANDCALIBRATIONOFFSE

22、TADDERGAINCONTROLDIGITALFINE CLAMPPROGRAMMABLEDELAYCP CSC ANDDECIMATIONFILTERSAVCODEINSERTIONSTANDARDIDENTIFICATIONSYNC EXTRACT(ESDP)MACROVISIONAND CGMS DETECTIONSYNC SOURCEAND POLARITYDETECTAUDIO OUTPUT FORMATTERAP0MCLKSCLKAP1AP2AP3AP4AP5FASTSWITCHINGBLOCK + HDMI DECODE+ MUXRXB_5V / HPDBRXA_5V / HP

23、DA5V DETECT AND HPDCONTROLLERRXD_5V / HPDDRXC_5V / HPDCHDCPEEPROMDEEP COLORCONVERSIONDDCB_SDA / DDCB_SCLDDCC_SDA / DDCC_SCLDDCD_SDA / DDCD_SCL(A)(B)(C)(A)(B)(C)(D)INTERRUPTCONTROLLERTTX_SDA / TTX_SCLDECIMATIONFILTERSHDMI ETHERNET CHANNEL&AUDIO RETURN CHANNELHEAC_2HEAC_1SPDIF_INE1_TX/E1_RXE2_TX/E2_RX

24、 Figure 2. Detailed Functional Block Diagram AVR 2650 AVR 2650 harman/kardonharman/kardon 123ADV7844 PRELIMINARY Rev. PrBC | Page 12 of 35 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1234567891011121314151617181920212223AGNDVS/FIELDE2_TX+E2_RX+TVDDRXD_2-RXD_1-RXD_0-RXD_C-HEAC_2-TVDDRXC_2-RXC_1-RXC_0

25、-RXC_C-TVDDRXB_2-RXB_1-RXB_0-RXB_C-HEAC_1-GNDABHS/CSFIELD/DEE2_TX-E2_RX-TVDDRXD_2+RXD_1+RXD_0+RXD_C+HEAC_2+TVDDRXC_2+RXC_1+RXC_0+RXC_C+TVDDRXB_2+RXB_1+RXB_0+RXB_C+HEAC_1+GNDBCP0P1E1_TX+E1_RX+TVDDPWRDN1PWRDN2HPA_DRXD_5VRXC_5VTVDDGNDGNDGNDGNDGNDGNDTVDDTVDDTVDDTVDDTVDDTVDDCDP2P3E1_TX-E1_RX-TVDDSYNC_OUT

26、CECHPA_CRXB_5VHPA_BTVDDRXA_5VHPA_ADDCD_SDADDCD_SCL DDCC_SDADDCC_SCLRTERMDDCB_SDA DDCB_SCLTVDDRXA_2+RXA_2-DEDVDDIODVDDIOGNDGNDDDCA_SDACVDDRXA_1+RXA_1-EFP5P4EP_MISOEP_MOSIDDCA_SCLCVDDRXA_0+RXA_0-FG-C_AXR+C_AXRDDVCLCS_AGVCVDDCVDDCVDDDNGDNG2TSET1TSETDNGDNGDNGDNGKCS_PESC_PE6P7PGHDDVCADS_AGVCVDDCVDDCVDDDN

27、GDNGDNGDNGDNGDNGDNGDNGLCS_XTTADS_XTT8P9PHJDNGDNG3TSETDDVPDNGDNGDNGDNGDNGDNGDNGDNGDNGDNGDNG0PAKLCM01P11PJKPLATXNLATXDNGDDVPDNGDNGDNGDNGDNGDNGDNGDNGDNGDNGDDVKLCS5PA21P31PKLDNGDNGDNGDNGDNGDNGDNGDNGDNGDNGDNGDNGDNGDNGDDVDNGDNGOIDDVDOIDDVDLMPFERNFERDNGDNGDNGDNGDNGDNGDNGDNGDNGDNGDNGDNGDDV3PA4PA41P51PMNDDVA

28、DDVADDVADDVADNGDNGDNGDNGDNGDNGDNGDNGDNGDNGDDV1PA2PA61P71PNP21NIA11NIADDVADDVADNGDNGDNGDNGDNGDNGDNGDNGDNGDNGDDVADSLCS91P81PPRDNGDNGDNGDNGDNGDNGDNGDNGDNGDNGDDV1TNI4TSET12P02PHS_IN2/TRI7 VS_IN2/TRI8SYNC4AIN10RTDNGDNGDNGDNGDNGDNGDNGDNGDNGDNGDNGDNGDNGDNGDDV2TNI5TSET32P22PTU8NIA9NIA3IRT4IRTDNGDNGDNGDDVDDV

29、DDVDDVDDVDDVDDVDDVOIDDVDOIDDVDOIDDVDOIDDVDUVLLCP24RESETAVLINKTRI1TRI2SYNC3AIN7VWP25P26SPDIF_INAVDDAVDDAVDDAVDDWYP27P28GNDGNDGNDVDD_SDRAM SDRAM_A11 SDRAM_A6 SDRAM_A2 SDRAM_CS SDRAM_LDQSGNDSDRAM_DQ6 SDRAM_DQ2 SDRAM_DQ15 SDRAM_DQ11 SDRAM_CKE VDD_SDRAMGNDAOUTNCAIN5AIN6YAAP29P30GNDGNDGNDVDD_SDRAM SDRAM_A

30、9 SDRAM_A5 SDRAM_A1SDRAM_RAS SDRAM_DQ7GNDSDRAM_DQ5 SDRAM_DQ1 SDRAM_DQ12 SDRAM_DQ8 SDRAM_CKVDD_SDRAMGNDNCNCSYNC2AIN4AAABP31P32P34GNDDVDDIOSDRAM_A8 SDRAM_A4 SDRAM_A0 SDRAM_BA1SDRAM_CAS VDD_SDRAM SDRAM_DQ4 SDRAM_DQ0 SDRAM_DQ13 SDRAM_DQ9 SDRAM_CKN VDD_SDRAMGNDSYNC1HS_IN1/TRI5 VS_IN1/TRI6GNDABACGNDP33P35

31、GNDDVDDIOSDRAM_A7 SDRAM_A3 SDRAM_A10 SDRAM_BA0 SDRAM_WE VDD_SDRAM SDRAM_DQ3 SDRAM_VREF SDRAM_DQ14 SDRAM_DQ10 SDRAM_UDQS VDD_SDRAMGNDAIN1AIN2AIN3GNDAC1234567891011121314151617181920212223NCNCNCNCNCNCNC Figure 7. Pin Configuration AVR 2650 AVR 2650 harman/kardonharman/kardon 124 PRELIMINARY ADV7844 Re

32、v. PrC| Page 13 of 35 Table 6. Function Descriptions Pin No. Mnemonic Type Description A1 GND Ground Ground A2 VS/FIELD Digital video output VS is a vertical synchronization output signal. FIELD is a field synchronization output signal in all interlaced video modes. VS or FIELD can be configured for

33、 this pin. A3 E2_TX+ Digital output Digital Output Channel 2 True of Ethernet Interface A4 E2_RX+ Digital input Digital Input Channel 2 True of Ethernet Interface A5 TVDD Power Terminator Supply Voltage (3.3 V). A6 RXD_2- HDMI input Digital Input Channel 2 Complement of Port D in the HDMI Interface.

34、 A7 RXD_1- HDMI input Digital Input Channel 1 Complement of Port D in the HDMI Interface. A8 RXD_0- HDMI input Digital Input Channel 0 Complement of Port D in the HDMI Interface. A9 RXD_C- HDMI input Digital Input Clock Complement of Port D in the HDMI Interface. A10 HEAC_2- HDMI input/output HDMI E

35、thernet and Audio Return Channel (HEAC) Complement Channel 2 in HDMI Interface A11 TVDD Power Terminator Supply Voltage (3.3 V). A12 RXC_2- HDMI input Digital Input Channel 2 Complement of Port C in the HDMI Interface. A13 RXC_1- HDMI input Digital Input Channel 1 Complement of Port C in the HDMI In

36、terface. A14 RXC_0- HDMI input Digital Input Channel 0 Complement of Port C in the HDMI Interface. A15 RXC_C- HDMI input Digital Input Clock Complement of Port C in the HDMI Interface. A16 NC No connect No Connect. A17 TVDD Power Terminator Supply Voltage (3.3 V). A18 RXB_2- HDMI input Digital Input

37、 Channel 2 Complement of Port B in the HDMI Interface. A19 RXB_1- HDMI input Digital Input Channel 1 Complement of Port B in the HDMI Interface. A20 RXB_0- HDMI input Digital Input Channel 0 Complement of Port B in the HDMI Interface. A21 RXB_C- HDMI input Digital Input Clock Complement of Port B in

38、 the HDMI Interface. A22 HEAC_1- HDMI input/output HDMI Ethernet and Audio Return Channel (HEAC) Complement Channel 1 in HDMI Interface A23 GND Ground Ground B1 HS/CS Digital video output HS is a horizontal synchronization output signal. CS (composite synchronization) signal is a single signal conta

39、ining both horizontal and vertical synchronization pulses. B2 FIELD/DE Miscellaneous digital DE (data enable) is a signal that indicates active pixel data. FIELD is a field synchronization output signal in all interlaced video modes. DE or FIELD can be configured for this pin. B3 E2_TX- Digital outp

40、ut Digital Output Channel 2 Complimentary of Ethernet Interface B4 E2_RX- Digital input Digital Input Channel 2 Complimentary of Ethernet Interface B5 TVDD Power Terminator Supply Voltage (3.3 V). B6 RXD_2+ HDMI input Digital Input Channel 2 True of Port D in the HDMI Interface. B7 RXD_1+ HDMI input

41、 Digital Input Channel 1 True of Port D in the HDMI Interface. B8 RXD_0+ HDMI input Digital Input Channel 0 True of Port D in the HDMI Interface. B9 RXD_C+ HDMI input Digital Input Clock True of Port D in the HDMI Interface. B10 HEAC_2+ HDMI input/output HDMI Ethernet and Audio Return Channel (HEAC)

42、 True Channel 2 in HDMI Interface B11 TVDD Power Terminator Supply Voltage (3.3 V). B12 RXC_2+ HDMI input Digital Input Channel 2 True Of Port C in the HDMI Interface. B13 RXC_1+ HDMI input Digital Input Channel 1 True Of Port C in the HDMI Interface. B14 RXC_0+ HDMI input Digital Input Channel 0 Tr

43、ue Of Port C in the HDMI Interface. B15 RXC_C+ HDMI input Digital Input Clock True Of Port C in the HDMI Interface. B16 NC No Connect No Connect. B17 TVDD Power Terminator Supply Voltage (3.3 V). B18 RXB_2+ HDMI input Digital Input Channel 2 True of Port B in the HDMI Interface. B19 RXB_1+ HDMI inpu

44、t Digital Input Channel 1 True of Port B in the HDMI Interface. B20 RXB_0+ HDMI input Digital Input Channel 0 True of Port B in the HDMI Interface. B21 RXB_C+ HDMI input Digital Input Clock True of Port B in the HDMI Interface. AVR 2650 AVR 2650 harman/kardonharman/kardon 125ADV7844 PRELIMINARY Rev.

45、 PrBC | Page 14 of 35 Pin No. Mnemonic Type Description B22 HEAC_1+ HDMI input/output HDMI Ethernet and Audio Return Channel (HEAC ) True Channel 1 in HDMI Interface B23 GND Ground Ground C1 P0 Digital video output Video Pixel Output Port. C2 P1 Digital video output Video Pixel Output Port. C3 E1_TX

46、+ Digital output Digital Output Channel 1 True of Ethernet Interface C4 E1_RX+ Digital input Digital Input Channel 1 True of Ethernet Interface C5 TVDD Power Terminator Supply Voltage (3.3 V). C6 PWRDN1 Miscellaneous digital Controls the Power-Up of the ADV7844. Should be connected to a digital 3.3

47、V I/O supply to power up the ADV7844. C7 PWRDN2Test pin This pin should be connected to the ground. C8 HPA_D Miscellaneous digital Hot Plug Assert signal output for HDMI port D. C9 RXD_5V HDMI input 5 V Detect Pin for Port D in the HDMI Interface. C10 RXC_5V HDMI input 5 V Detect Pin for Port C in t

48、he HDMI Interface. C11 TVDD Power Terminator Supply Voltage (3.3 V). C12 GND Ground Ground C13 GND Ground Ground C14 GND Ground Ground C15 GND Ground Ground C16 GND Ground Ground C17 GND Ground Ground C18 TVDD Power Terminator Supply Voltage (3.3 V). C19 TVDD Power Terminator Supply Voltage (3.3 V).

49、 C20 TVDD Power Terminator Supply Voltage (3.3 V). C21 TVDD Power Terminator Supply Voltage (3.3 V). C22 TVDD Power Terminator Supply Voltage (3.3 V). C23 TVDD Power Terminator Supply Voltage (3.3 V). D1 P2 Digital video output Video Pixel Output Port. D2 P3 Digital video output Video Pixel Output P

50、ort. D3 E1_TX- Digital output Digital Output Channel 1 Complimentary of Ethernet Interface D4 E1_RX- Digital input Digital Input Channel 1 Complimentary of Ethernet Interface D5 TVDD Power Terminator Supply Voltage (3.3 V). D6 SYNC_OUT Miscellaneous digital Sliced synchronization output. D7 CEC Digi