Arcam-AVR600-avr-sm维修电路原理图.pdf
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1、UAAVR600 Service manual issue 1.2 ARCAMRadioFans.CN 收音机爱 好者资料库This PCB provides the power for the unit through CON203: +5V_STBY 5V standby supply L118 RS232, L126 display (on in standby) +3V3 PW338 L122 PW338 supply (on in standby) 1V8D L122 PW338 supply (on in standby) +5V_1 general 5V supply +6V_1
2、 L156 DSP, L126 Display & L119 NET supply +40V_VFD L126 Display +15V linear +15V supply -15V linear -15V supply LK100 or the thermal switch from the power amp transformer is required to pass the live mains. SW101 switches between 230V & 115V. R101 & R102 are NTC parts to prevent inrush currents when
3、 the power amp is turned on. CON202 takes the Clk PSU sync signal from L121, Relay SW from L122 (to turn on the main supplies) and /AC present back to L122. /AC present is generated from the standby transformer secondaries with D200.D210 & TR200. This will prevent the unit from starting if it is not
4、 low. The standby transformer is rectified with DBR200 (GBU4K) to give UNREG_PW338 which is used for the 1V8D (REG206 LM2670), 3V3_PW338 (REG201 LM2670). The 12V for the relays to switch the secondaries are also generated from REG207 (LM7812) which is then regulated down to give +5V_STBY REG200 (LM7
5、805). When the signal Relay SW is taken high by the PW338, the secondaries of the system & power amp transformer are switched in (RLY101 & RLY102). This enables +15V, -15V (REG204 & REG205) & +5V_1 & +6V_1 (REG202 & REG203).L123AY Connection board and PSU RadioFans.CN 收音机爱 好者资料库This PCB selects betw
6、een one of five component video inputs & also provides the output connector for Zone 3 audio. IC100, IC101 & IC104 (LT1675CGN video buffers) require +5V & -5V. The +5V comes direct from L123 & -5V is generated locally from the -15V supply (from L123). Selection of the five inputs is via IC102 (74HCT
7、595D serial to parallel converter, controlled via SPI Clk, Data & Vcomp latch) and IC100, IC101, IC104. IC102 generates a /ENx signal which tri-states the output when high and enables the output when low. When low the input is selected with the SELx signal, high for input1, low for input2. Truth tab
8、le: EN0 SEL0 EN1 SEL1 EN2 SEL2 0 0 1 X 1 x SAT 0 1 1 X 1 x AV 1 x 0 0 1 x VCR 1 x 0 1 1 x DVD 1 x 1 x 0 1 PVR 1 x 1 x 1 x BLANK* *When component input is not used, BLANK should be selected. SKT101 provides zone 3 audio output. L113AY Component Input Output boardThis PCB selects between one of five s
9、-video & composite video inputs for the main input & zone 2 video. It also controls the volume control for Zone 2 & 3. The main input video is selected using IC200 (LA73031V video mux) under the control of IC205 & IC208 (74HC595 serial to parallel converters, controlled by SPI Clk, Data & Vid IO Mux
10、 Latch). Inputs are selected using INSEL1, INSEL2, INSEL3 (Z2 INSEL1, Z2INSEL2, Z2INSEL3 for Zone 2 via IC203 LA73031V video mux). As there is only one sync separator within each LA73031V, it is necessary to select if this is used for S-video or composite (this means that once composite video is sel
11、ected as the source, it is not possible to autodetect S-video) - SYNC CTL selects, low = Svideo, high = composite. There are two buffered (IC201 & IC202 BA7623F video buffers) tape outputs, VCR & PVR which can be muted with VCR Mute & PVR Mute respectively through a transistor network. Each output i
12、s muted when that input is selected to prevent feedback, otherwise the output is a copy of the composite or S-video signal going to the main zone. Zone 2 video is buffered through IC204 (BA7623F video buffer) and can also be mute, if required using the signal Z2Vid Mute & a transistor network. When
13、S-video or composite inputs are not used, V MUX STBY should be asserted high. Note: this will disable both the main Zone & Zone 2 S-video & composite muxes. Video Input Truth table: (Z2)INSEL1 (Z2)INSEL2 (Z2)INSEL3 (Z2)SYNCCTL 0 0 0 1 AV comp 0 0 1 1 SAT comp 0 1 0 1 DVD comp 0 1 1 1 PVR comp 1 0 0
14、1 VCR comp 0 0 0 0 AV S-vid 0 0 1 0 SAT S-vid 0 1 0 0 DVD S-vid 0 1 1 0 PVR S-vid 1 0 0 0 VCR S-vid Volume control for Zone 2 & 3 uses IC300 & IC301 (BD3812F volume controls) via a two-wire interface (Zone SPI Clk & Zone SPI Data). IC300 has address D2, D1=1, IC301 has address D2, D1=0. The volume c
15、ontrols can be muted from IC208 (Serial to parallel converter) using Z2 vol mute or Z3 vol mute. The outputs are also relay controlled for powerup/down with Z2 Mute & Z3 Mute directly from the PW338 using RLY300 & RLY301 as shunt relays. The +7VA & -7VA required for the BD3812F volume controls is de
16、rived using REG300 (LM1117) & REG301 (LM337LZ) from the +15V & -15V from L123. L114AY Video input output This PCB selects on of 8 external digital inputs or one of two internal digital inputs & generates BClk, WClk & MClk for the DSP (see L156) & DAC (see L117). It also generates the clocks for the
17、ADC (see L116) when the unit is in ADC mode. The CD, AV & DVD inputs use coaxial connector SKT100 and feed into IC200 & IC201 (DS9637ACM buffers). The Tape, SAT, VCR & PVR inputs use optical connectors RX100, RX101, RX102, RX103. The outputs are padded down to give 3v3 outputs. There is also the Aux
18、 input which can be selected (see L117), the Net input (see L119) and the HDMI SPDIF (see L122). One of these inputs is then selected using IC202 & IC203 (74HC151 8-1 mux) under the control of IC204 (74HC595D serial to parallel converter) controlled by AN SPI Clk, AN SPI Data & Dig Mux Latch. The se
19、lected input is fed to IC100 (WM8805 SPDIF Rx/Tx) which is controlled from the PW338 via AN SCL, AN SDA & SPDIF /RESET. IC100 generates 8805MClk, 8805BClk & 8805WClk. Also, SPDIF Out which is a de-jittered SPDIF stream which is then buffered by IC103 part A, B, C & D (parts E & F are unused) to give
20、 both the optical output (TXC100) & 75ohmcoaxial output (SKT101). The selected input is also fed to IC205 part A (74HC123D monostable, part B unused) which gives a high output from pin 13 (SPDIF_PRESENT to the PW338) if an SPDIF signal is present. BClk=64* WClk MClk=128*WClk (192kHz/176.4kHz), 256*W
21、Clk (96kHz/88.2kHz), 512*WClk (48kHz/44.1kHz) this clock is used by the PSU to synchronise the switchers. IC105 (XC95C36 Xilinx) generates a pre-delayed SPDIF stream from the HDMI clocks (only MClk & WClk used) as the HDMI SPDIF is turned off during HD audio transfer & the WM8805 does not have a zer
22、o delay PLL. IC104 (74HCT157 Quad 2-1 mux) can also be used to re-direct the clocks from the HDMI into the system. IC100 (WM8805) can also operate in master mode to generate clocks for the ADC when processing an analogue input. 3V3D is generated locally on the PCB from 5V_1 using REG200 (LM1117).L11
23、5AY Digital Input Output board This PCB selects the analogue input for the main zone & Zone 2/3 and also digitises the analogue input for processing by the DSP / transmission over SPDIF. One of seven phono inputs (Tape, CD, AV, DVD, SAT, VCR, PVR), Aux (external) input (see L127), AM/FM & DAB(intern
24、al)/Sirius(external) inputs (see L118), Net (internal) input (see L119) and Phono (see L117). The input for the main zone is selected using IC200, IC208, IC205, IC209 (74HC4051D 8-1 mux) under the control of IC101 & IC102 (74HC595 serial to parallel converter), controlled by AN SPI Data, AN SPI Clk
25、& A In Mux Latch. The muxes operate on the virtual earth of IC203 part A (left channel) & IC206 part A (right channel), both NJM2114 op amps, inverting the signal. Part B of these two op amps re-invert the signal (correct phase) and this output is used by the ADC & the direct path Main L & Main R. I
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