Onkyo-FR155-cdmd-sm维修电路原理图.pdf

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1、FR-155 Ref. No. 3662 MODEL FR-155 092000 CD/MD TUNER AMPLIFIER Silver model UDT120V AC, 60Hz UGT220 -230V AC, 50/60Hz SAFETY-RELATED COMPONENT WARNING! COMPONENTS IDENTIFIED BY MARK ON THE SCHEMATIC DIAGRAM AND IN THE PARTS LIST ARE CRITICAL FOR RISK OF FIRE AND ELECTRIC SHOCK. REPLACE THESE COMPONE

2、NTS WITH ONKYO PARTS WHOSE PART NUMBERS APPEAR AS SHOWN IN THIS MANUAL. MAKE LEAKAGE-CURRENT OR RESISTANCE MEASUREMENTS TO DETERMINE THAT EXPOSED PARTS ARE ACCEPTABLY INSULATED FROM THE SUPPLY CIRCUIT BEFORE RETURNING THE APPLIANCE TO THE CUSTOMER. TABLE OF CONTENTS Specifications - Caution on repla

3、cement of optical pickup - Protection of eyes from laser beam during servicing - Laser Warning Label- Service procedures - Front panel view - Connecting to Other Components- Remote controller - Setting the day of the Week and the Time- IC Block diagram and descriptions - Microprocessor Connection Di

4、agram- Microprocessor Terminal Description- Operation of the Microprocessor- MD Mechanism Exploded view- MD Mechanism Disassembly - MD Mechanism Reassembly - MD Adjustment Procedures - MD Mount View / Messages- CD Mechanism Exploded View - CD Adjustment Procdedure- Clock Adjustment Procdedure- Handl

5、ing of Pickup- Chassis Exploded View Parts List- Chassis Exploded View - Block Diagram- Block Diagram (Power Supply Section)- Schematic Diagram (Amplifire Section)- Printed Circuit Board View 1- Schematic Diagram (CD normally GND. TEST pin; normally GND. Charge pump output for the wide-band EFM PLL.

6、 VCO2 oscillation input for the wide-band EFM PLL. VCO2 oscillation output for the wide-band EFM PLL. VCO2 control voltage input for the wide-band EFM PLL. Master PLL charge pump output. Master PLL (slave = digital PLL) filter output. Master PLL filter input. Analog GND. Master VCO control voltage i

7、nput. Analog power supply (+5V). EFM signal input. Constant current input of the asymmetry circuit. Asymmetry comparator voltage input. EFM full-swing output (low = VSS, high = VDD). D/A interface. LR clock output f = Fs. LR clock input. D/A interface. Serial data output (twos complement, MSB first)

8、. D/A interface. Serial data input (twos complement, MSB first). D/A interface. Bit clock output. D/A interface. Bit clock input. GND Power supply (+5V). XUGF output. Switched to MNT1 or RFCK output by a command. XPLCK output. Switched to MNT0 output by a com- mand. GFS output. Switched to MNT3 or X

9、RAOF output by a command. C2PO output. Switched to GTOP output by a com- mand. Crystal selector input. Low: 16.9344MHz; high: 33.8688MHz. 4.2336MHz output. 1/4 frequency-divided VCKI out- put in CAV-W mode. Digital Out output. Outputs a high signal when the playback disc has emphasis, and a low sign

10、al when there is no emphasis. Inputs a high signal when de-emphasis is on, and a low signal when de-emphasis is off. WFCK output. Outputs a high signal when either subcode sync S0 or S1 is detected. Sub P to W serial output. SBSO readout clock input. GND Power supply (+5V). Mute input. Active when h

11、igh. Analog GND. Analog power supply (+5V). Left-channel analog output. Left-channel operational amplifier input. Left-channel LINE output. Analog GND. Power supply for master clock. Crystal oscillation circuit input. Input the external master clock via this pin. Crystal oscillation circuit output.

12、GND for master clock. Analog GND. Right-channel LINE output. Right-channel operational amplifier input. Right-channel analog output. Analog power supply (+5V). Analog GND. System reset. Reset when low. Power supply (+5V). 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

13、69 70 71 72 73 74 75 76 77 78 79 80 O I O O O O I O O O I O O O I I O I O I O O I O I BCK BCKI VSS VDD XUGF XPCK GFS C2PO XTSL C4M DOUT EMPH EMPHI WFCK SCOR SBSO EXCK VSS VDD SYSM AVSS AVDD AOUT1 AIN1 LOUT1 AVSS XVDD XTAI XTAO XVSS AVSS LOUT2 AIN2 AOUT2 AVDD AVSS XRST VDD FR-155 10 VEEVEE TM3 TM5 TM

14、2 TM3 FSET TM6 TM4 VCCVCC VCC ISET TN1-7PS1-4 TTL IIL IIL TTL CC1 DFCT1 DFCT IIL TTL VCC CC1 CC2 FOK RF-I CP CB VCC VEE VEE VEE LEVEL S MIRR MIRR TGFL LPC IIL DATA REGISTER INPUT SHIFT REGISTER ADDRESS DECODER SENS SELECTOR OUTPUT DECODER DFCTOIFB1-6 BAL1-4 TOG1-4 FS1-4TG1-2 VCC FS1 FS2 Charge up TG

15、2 SRCH TGU TG2 FSET TA-M VEE FLB FE-O FE-M FOCUS PHASE COMPENSATION TRACKING PHASE COMPENSATION FOH FOL TGH TGL BALH BALL ATSC TZC FZC LDON LPCL FOK VCC FO.BIAS WINDOW COMP. RF SUMMING AMP RFTC RF-M RF-O PD LD VEE VCC APC LASER POWER CONTROL VEE VCC FE AMP IFB1 IFB2 IFB3 IFB4 IFB5 IFB6 VEE TRK.GAIN

16、WINDOW COMP TM1 TG1 FS4 DFCT TA-O FEO FEI FDFCT FGD DFCT E-F BALANCE WINDOW COMP. TGFL BAL3 BAL4 PD1 IV AMP FZC COMP. VEE VCC VCC TZC COMP. ATSC WINDOW COMP. TOG1 TOG2 TOG3 TOG4 BAL1 BAL2 VEE E IV AMP F IV AMP PD2 IV AMP PD1 PD2 FE-BIAS F E EI TEO VEE LPFI TEI ATSC TZC TDFCT VC FZCSL-P SL-M SL-O ISE

17、T VCC XLT CLK LOCK DATA XRST C.OUT SENS1 SENS2 12345678910111213 14 15 16 17 18 19 20 21 22 23 24 25 26 27282930313233343536373839 40 41 42 43 44 45 46 47 48 49 50 51 52 Q101:CXA1992BR (RF Signal Processing Servo Amplifier) Block Diagram FR-155 11 Pin Description Pin No. Symbol I/O Description Pin N

18、o. Symbol I/O Description Focus error amplifier output. Connected internally to the window comparator input for bias adjustment. 1FEO O 2FEIFocus error input. I 3 4 FDFCT ICapacitor connection pin for defect time constant. FGD IGround this pin through a capacitor for cutting the focus servo high-fre

19、quency gain. 5FLBIExternal time constant setting pin for boosting the focus servo low-frequency. 6FE_OOFocus drive output. 7FE_M IFocus amplifier inverted input. 8SRCHIExternal time constant setting pin for generating focus search waveform. 9TGUIExternal time constant setting pin for switching track

20、- ing high-frequency gain. 10TG2IExternal time constant setting pin for switching track- ing high-frequency gain. 11FSETIPeak frequency setting pin for focus and tracking phase compensation amplifier. 12TA_MITracking amplifier inverted input. 13TA_OOTracking drive output. 14SL_PISled amplifier non-i

21、nverted input. 16SL_OOSled drive output. 15SL_MISled amplifier inverted input. F I-V and E I-V amplifier inverted input. Connect these pins to photo diodes F and E. 17ISETIConnect an external capacitance to set the current which determines the Focus search, Track jump, and Sled kick heights. 18VCCIP

22、ositive power supply. 19LOCKIThe sled overrun prevention circuit operates when this pin is Low. (no pull-up resistance) 20CLKI 22DATAI 21XLTI Serial data transfer clock input from CPU. (no pull-up resistance) Latch input from CPU. (no pull-up resistance) Serial data input from CPU. (no pull-up resis

23、tance) 23XRSTIReset input; resets at Low. (no pull-up resistance) 24C. OUTOTrack number count signal output. 25SENS1OOutputs FZC, DFCT1, TZC, BALH, TGH, FOH, ATSC, and others according to the command from CPU. 26SENS2OOutputs DFCT2, MIRR, BALL, TGL, FOL, and others according to the command from the

24、CPU. 27FOKOFocus OK comparator output. 28 CC2IInput for the defect bottom hold output with capa- citance coupled. 29CC1ODefect bottom hold output. Connected internally to the interruption comparator input. 30CBIConnection pin for defect bottom hold capacitor. 31CPI 32RF_II 33RF_OO 34RF_MI Connection

25、 pin for MIRR hold capacitor. MIRR comparator non-inverted input. Input for the RF summing amplifier output with capa- citance coupled. RF sunning amplifier output. Eyepattern check point. RF summing amplifier inverted input. The RF amplifier gain is determined by the resistance connected between th

26、is pin and RFO pin. 35RFTCIExternal time constant setting pin during RF level control. 36LDOAPC amplifier output. 37PDI APC amplifier input. 38PD1I 39PD2I RF I-V amplifier inverted input. Connect these pins to the photo diode A + C and B + D pins. 40FE_BIASIBias adjustment of focus error amplifier.

27、Leave this pin open for automatic adjustment. 41FI 42IE 43EI I-V amplifier E gain adjustment. (When not using automatic balance adjustment) 44VEE Negative power supply. 45TEOOTracking error amplifier output. E-F signal is output. 46LPFIIComparator input for balance adjustment. (Input from TEO throug

28、h LPF) 47TEI ITracking error input. 48ATSC I Window comparator input for ATSC detection. 49TZC I Tracking zero-cross comparator input. 50TDFCTICapacitor connection pin for defect time constant. 51VCO(VCC + VEE)/2 direct voltage output. 52FZCIFocus zero-cross comparator input. FR-155 12 Vcc 1 2 3 4 5

29、 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Level shift 4 BTL AMP 4 Level shift 1 BTL AMP 1 BTL AMP 3 BTL AMP 2 Level shift 3 Level shift 2 RESET Regulator Pin No.Pin NameDescription (Function) VCC Power supply (shorted with pin 30) MuteON/OFF control for all BTLAMP outpu

30、ts VIN1BTLAMP 1 input VG1BTLAMP 1 input (for gain control) BTLAMP 1 output (non-inverting side) BTLAMP 1 output (inverting side) GNDGND (minimum electric potential) GNDGND (minimum electric potential) GNDGND (minimum electric potential) VO3BTLAMP 2 output (inverting side) VO4BTLAMP 2 output (non-inv

31、erting side) VG2BTLAMP 2 input (for gain control) VIN2BTLAMP 2 input REG OUTConnection for collector of external transistor (PNP); 5 V supply output REG INConnection for base of external transistor (PNP) RESReset output CDReset output delay time setting (with capacitor) VIN3BTLAMP 3 input VG3BTLAMP

32、3 input (for gain control) VO5BTLAMP 3 output (non-inverting side) VO6BTLAMP 3 output (inverting side) GNDGND (minimum electric potential) GNDGND (minimum electric potential) GNDGND (minimum electric potential) VO7BTLAMP 4 output (inverting side) VO8BTLAMP 4 output (non-inverting side) VG4BTLAMP 4 i

33、nput (for gain control) VIN4BTLAMP 4 input VREFReferencevoltage input for level shift circuit VCCPower supply (shorted with pin 1) Vcc Vref VIN4 VG4 Vo8 Vo7 GND GND GND Vo6 Vo5 VG3 VIN3 CD RES Vcc Mute VIN1 VG1 Vo1 Vo2 GND GND GND Vo3 Vo4 VG2 VI2 Reg OUT Reg IN Q102:LA6541D (CD 4-channel BTL Driver

34、) + (4) (3) (5) (6) (12) (11) (16) (1) (2) (10)(9) Measurement circuit Differential decoder Bi-phase decoder PLL 1187.5Hz PLL 57kHz RDS/ARI Reference clock (13)(14) (7)(8) 120k 100k 100k Analog Power supply Digital power supply anti-aliasing filter 8ch Switched capacitor filter Comparator RCLK QUAL

35、RDATA T2T1 XOX1 VSS2 VDD2 VSS1 VDD1 VREF MUX VSS3CMP Pin name Demodulator quality Demodulator data Reference voltage Input Analog power supply GND Comparator input Test input Digital power supply Crystal oscillor - Demodulator clock Function Good data : High , bad data : Low Refer to output data tri

36、mming 1/2 VDD1 (refer to input/output circuits) Composite signal input 4.5V to 5.5V - C-junction Open or connected to ground 4.5V to 5.5V Connects to 4.332MHz oscillator (refer to input/output circuit) - 1187.5Hz clock Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol QUAL RDATA Vref MUX VDD1 Vs

37、s1 Vss3 CMP T2 T1 VDD2 Vss2 XI XO (NC) RCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Vo1 Vo2 Q171:BU1923(RDS Decoder) FR-155 13 Q752:M66004F (FL Tube Driver) Segment output circuit CG ROM (35bit 160) CG RAM (35bit 16) DecoderDecoder Display code register Seria

38、l receive circuit Code / command control circuit Display control register Clock generator Display controller Digit output circuit Output port (2bits) code write RAM write code select SEG00 SEG26 SEG35 SEG27 Segment output P0 P1 Output ports Chip select input CS DIG00 DIG11 DIG12 DIG15 Digit outputs

39、Clock input XIN Clock output XOUT Reset input RESET Shift clock input Serial data input SCK SDATA 18 16 15 13 14 17 22 21 23 33 31 59 61 1 64 12 These pins are used to connect to digit pins of VFD. RESETReset inputThis pin is used to initialize the internal state on the M66004 CSChip select input L

40、: communication with the MCU is possible. H : any instruction from teh MCU is neglected. SCKShift select inputAt the rising edge from LtoH , input data is shifted. SDATASerial data inputCharacter code or command data to display is input from MSB. XIN, XOUT Clock input Clock output Set oscillation fr

41、equency DIG00 - DIG15 Digit output SEG00 - SEG35 Segment output P0,PIOutput port (static operation) VSS GND VPNegative power supply for VFD drive. VCC1 VCC2 Positive power supply for internal logic. Positive power supply for high-pressure-resistant output port. SymbolPin nameFunctionPin No. 13 14 15

42、 16 21, 22 1-12 61-64 23-31 33-59 17,18 19 60 22 32 These pins are used to connect to segment pins of VFD. FR-155 Q751:BJ780GNK(FL Tube) SLEEPSOURCEC DTIMERM DM D CH C D C D ONCE W.DAY W.END REC L R -40-20-100 OVER-6-2 MUTINGDIGITALCHAIN REPEAT DISC TRACK ELAPSEDREMAINTITLE RDS MONO AUTO STEREOTUNED

43、 1 TR MEMORY RANDOM LEVEL - SYNC -M D DUBTOC L R -40-20-100 OVER-6-2- C DM D S3S4 1-1 2-1 3-1 4-1 5-1 1-2 2-2 3-2 4-2 5-2 1-7 2-7 3-7 4-7 5-7 1-6 2-6 3-6 4-6 5-6 1-3 2-3 3-3 4-3 5-3 1-5 2-5 3-5 4-5 5-5 1-4 2-4 3-4 4-4 5-4 (12G 1G) (14G) (13G) B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B1 B2 B3 B4 B

44、5 B6 B7 B8 B9 B10 B11 S1 Col-1Col-2Dp 13G 12G 11G 10G 9G 8G 7G 6G 5G 4G 3G 2G 1G S2 14G P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 14G13G12G11G10G9G8G7G6G5G4G3G2G1G B1 B8 B12 B19 S1 B2 B9 B13 B20 S2 B3 B10 B1

45、4 B21 OVER B4 B11 B15 B22 SLEEP B5 ONCE B16 W.DAY W.END B6 REC S.BASS MUTING B18 LEVEL-SYNC B7 DIGITAL - B17 - 1-1 2-1 3-1 4-1 5-1 1-2 2-2 3-2 4-2 5-2 1-3 2-3 3-3 4-3 5-3 1-4 2-4 3-4 4-4 5-4 1-5 2-5 3-5 4-5 5-5 1-6 2-6 5-7 4-7 3-7 2-7 1-7 5-6 4-6 3-6 SOURCE 1-1 2-1 3-1 4-1 5-1 1-2 2-2 3-2 4-2 5-2 1-3 2-3 3-3 4-3 5-3 1-4 2-4 3-4 4-4 5-4 1-5 2-5 3-5 4-5 5-5 1-6 2-6 5-7 4-7 3-7 2-7 1-7 5-6 4-6 3-6 - 1-1 2-1 3-1 4-1 5-1 1-2 2-2 3-2 4-2 5-2 1-3 2-3 3-3 4-3 5-3 1-4 2-4 3-4 4-4 5-4 1-5 2-5 3-5 4-5 5-5 1-6 2-6 5-7 4-7 3-7 2-7