JVC-MXG50-cs-sm维修电路原理图.pdf
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1、SERVICE MANUAL COMPACT COMPONENT SYSTEM No.20978 Jul. 2001 COPYRIGHT 2001 VICTOR COMPANY OF JAPAN, LTD. MX-G50 MX-G50 Area Suffix US UW UY Singapore Brazil,Mexico,Peru Argentina Contents Safety Precautions Important for laser products Preventing static electricity Disassembly method Wiring connectio
2、n Adjustment method Flow of functional operation until TOC read Maintenance of laser pickup Replacement of laser pickup Trouble shooting Description of major ICs 1-2 1-3 1-4 1-5 1-20 1-21 1-25 1-26 1-26 1-27 1-3043 DISC SKIP VOLUME VOLUME + RMSMXG50U REMOTE CONTROL STANDBY/ON 123 456 789 10+10 SLEEP
3、 SUBWOOFER LEVEL SOUND MODE FM MODE TAPE A/B FADE MUTINGFM/AM AUX / CD TAPE zzzzzECHO CANCEL /DEMO PRESET COMPU PLAY CONTROL PLAY 5V) -Check the main PCB RIC1(L4959) -Check the front PCB UD13(IN4002) -Check the main PCB; RBD1(PBL403) RD8(IN5392) -Check the power PCB; Fuse P/T, RFS2, RFS5, RFS6 -Chec
4、k the main PCB; RR7, RC7, RZD4, RR6 RR5, RR4, RC8, RD3 Check the B+, B- power source RBD1, RBD2, RW2 Check the power PCB Fuse, P/T, RFS2, RFS5, RFS6, RFS7, RFS8 Front PCB Does UX1(6MHz) oscillate? Check the main PCB RIC1(L4959) Check the AMP PCB AIC1, AIC2 Check headphone jack soldering condition Ch
5、eck the front PCB UIC( -com), UIC2(M66010GP) Check the AMP PCB AQ2L, 2R, AQ1,5,6,7 Remove it with remoconIs mute selected? Headphone jack short? NoNo No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Replase -com Replase UIC2(M66010) Front PCB When the power is ON H display at pin no.15(UI
6、C2) AQ2L, 2R, AQ1,2,3,4 Emitter B+? AMP PCB AIC1, pin no. 4,8,9,12 B+,B- normal? UIC1( -com)pin79 check the H? MX-G50 1-28 2. Tuner malfunction (FM/AM) 3. Tape malfunction MX-G50 1-29 4.CD MX-G50 1-30 2. Block diagram 5L9290 (IC201) : Digital signal processor for CDP 1. Pin layout DPLL CLV Servo LOC
7、K SMEF SMDP SMDS WDCK EFMI VCO1LF Timing Generator Micom Interface WFCK RFCK C4M XIN ISTAT MLT MDAT MCK MUTE Subcode Out EFM Demodulator ECC 16K SRAM Address Generator SQCK SBCK SOS1 SQDT SBDT Interpolator I/O Interface JITB LPF PWM SADTO LRCKO BCKO LCHOUT RCHOUT VHALF VREF 1-bit DAC Digital Out Dig
8、ital Filter C2PODATX SADTI LRCKI BCKI S5L9290X DSP+DAC 48-LQFP-0707 VSSA_PLL VCO1LF VSSD_PLL VDDD_PLL XIN XOUT EFMI LOCK SMEF C2PO JITB DATX VDDD3-5V VDDD2-3V SBCK SQDTSMON TESTV SMDS WDCK MUTE BCKI 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 131415161718192021222324 4847464544434
9、24140393837 VDDD1_5V VSSD1_5V LKFS LKFS RESETB MLT MDAT MCK ISTAT S0S1 SQCK VSSD2-3V SADTO LRCKO BCKO LRCKI SADTI VSSD_DAC VDDD_DAC RCHOUT VSSA_DAC VREF VHALF VDDA_DAC LRHOUT VDDA_PLL Description of major ICs MX-G50 1-31 3. Pin function(1/2) NO.NAMEI/OPin Description 1VSSA_PLL-Analog Ground for DPLL
10、 2VCO1LFOPump out for VCO1 3VSSD_PLL-Digital Ground Separated Bulk Bias for DPLL 4VDDD_PLL-Digital Power Separated Bulk Bias for DPLL (3V Power) 5VDDD1-5V-Digital Power (5V Power, I/O PAD) 6XINIXtal oscillator input (16.9344MHz) 7XOUTOXtal oscillator output 8VSSD1-Digital Ground (I/O PAD) 9EFMIIEFM
11、signal input 10LOCKOCLV Servo locking status output 11SMEFOLPF time constant control of the spindle servo error signal 12SMDPOPhase control output for Spindle Motor drive 13SMDSOSpeed control output for Spindle Motor drive 14WDCKOWord clock output (Normal Speed : 88.2KHz, Double Speed : 176.4KHz) 15
12、TESTVIVarious Data/Clock Input 16LKFSOThe Lock status output of frame sync 17C4MO4.2336MHz clock output 18RESETBISystem Reset at L 19MLTILatch signal input from Micom 20MDATISerial data input from Micom 21MCKISerial data receiving clock input from Micom 22ISTATOThe internal status output to Micom 23
13、S0S1OSubcode sync signal(S0+S1) output 24SQCKISubcode-Q data transfering bit clock input MX-G50 1-32 3. Pin function (2/2) NO.NAMEI/OFunction Description 25SQDTOSubcode-Q data serial output 26MUTEISystem mute at H 27VDDD2-3V-Digital Power (3V Power, Internal Logic) 28VSSD2-Digital Ground (Internal L
14、ogic) 28VDDD3-5V-Digital Power (5V Power, I/O PAD) 30SBCKISubcode data transfering bit clock 31JITBOInternal SRAM jitter margin status output 32C2POOC2 pointer output 33DATXODigital audio data output 34SADTOOSerial audio data output (48 slot, MSB first) 35LRCKOOChannel clock output 36BCKOOBit clock
15、output 37BCKIIBit clock input 38LRCKIIChannel clock input 39SADTIISerial audio data input (48 slot, MSB first) 40VSSD_DAC-Digital Ground for DAC 41VDDD_DAC-Digital Power for DAC (3V Power) 42RCHOUTORight-Channel audio output through DAC 43VSSA_DAC-Analog Ground for DAC 44VREFOReferance Voltage outpu
16、t for bypass 45VHALFOReferance Voltage output for bypass 46VDDA_DAC-Analog Power for DAC (3V Power) 47LCHOUTOLeft-Channel audio output through DAC 48VDDA_PLL-Analog Power for PLL (3V Power) MX-G50 1-33 BA4560 (AIC3, AIC4, AIC5, AIC6, AIC7, FIC4, JIC2, UIC3) : Op amp. 1.Pin layout + + 1 2 3 4 8 7 6 5
17、 OUT1 IN1 + IN1 VEE VCC OUT2 IN2 + IN2 1ch 2ch KA9258D (IC301) : 4-ch Motor driver 2827262524232221201918171615 1234567891011121314 GND GND 10K REGULATOR 10K 10K VCCVCC 10K 10K T S D 10K 10K 10K 50K MUTE +- LEVEL SHIFT -+ LEVEL SHIFT MX-G50 1-34 KA22291 1 2 3 4 5 6 7 8 9 10 11 12 1314151617181920212
18、22324 14 13 12 11 23 2221820191815 24 16 9 1 17 10234576 PRE 100k B-IN A-AN MUTE MUTE REC PB NF(2) PB IN(2) R/P SW SW IN(2) ALC OUT(2) PB OUT(2) Vcc Vcc REC GND PB OUT(1) INPUT REC.BIAS RECORE I.REF PLAYBACK I.REF PB.BIAS INPUT PRE 100k N.F R/P SW ALC TIME CONSTANT 100k NF PRE INPUT REC NF(2) REC IN
19、(2) REC IN(1) REC NF(1) ALC DET PRE INPUT N.F 100k MODE CONTROL /BIAS CIRCUIT A/B SELECT SW B-IN A-AN PB NF(1) PB IN(1) A/B SW PB MUTE REC GND IN(1) OUT(1) KA22291(JIC1) : PB/REC pre amp. 1.Pin layout 2.Block diagram MX-G50 1-35 Pin NumberPin NameI/OPin Function Descriptio n 1GND-Ground 2VO1OOutput
20、1 3VZ1-Phase compensation 4VCTLIMotor speed control 5VIN1IInput 1 6VIN2IInput 2 7SVCC-Supply voltage (Signal) 8PVCC-Supply voltage (Power) 9VZ2-Phase compensation 10VO2OOutput 2 12345678910 GNDVO1VZ1VCTLVIN1VIN2SVCCVO2PVCCVZ2 KA3082 DRIVER OUT PRE DRIVER LOGIC SWITCH TSD BIAS 12345678910 GNDVO1 VZ1V
21、CTL VIN1VIN2SVCC PVCCVZ2VO2 KA3082 (IC401, IC402) : Bi-directional DC motor driver 3.Block Diagram 1.Pin layout 2.Pin function MX-G50 1-36 RF amp & Servo signal processor 2. Block diagram 4 12 RF AGC & EQ Control Focus OK Detect Defect Detect Mirror Gen Center Voltage APC. Laser Control & LPC Tracki
22、ng Servo Loop - Gain & Phase Compensation - Track Jump - Offset Adjust - TZC Gen. Tracking Error (RW) I/V AMP RF & Focus Error (CD-RW) I/V AMP Hardware Logic - Auto-Sequencer - Fast Search - Febias, Focus Servo, Tracking Offset ADJ. - Tracking Balance & Gain Adjust - Interruption Detect - EFM Muting
23、 System Sled Servo & Kick Gen Spindle Servo LPF EFM Comparator Micom Data Interface Logic Decoder Focus Servo Loop - Gain & Phase Compensation - Focus Search - Offset Adjust - FZC Gen. EQO PD LD LPFT TEIO TZC& SSTOP ATSC TEO TEM SLP SLO SLM FEO FEM SPDLO SPDLM EQI RFO RFM EQC VREF PDE PDF PDBD PDAC
24、ISTAT MCK MDATA MLT RESET WDCK CLVI LOCK ASY EFM 5 45 46 44 43 6 7 8 9 10 11 14131516171918202221 24 23 30 29 25 26 27 28 29 36 33 34 35 37 38 39 4140424748123 EFMI DCCI DCC0 MCP DCB VCC/ VDD FRSH FSET FLB FGD FSI TGU S1L9226X TEO TEM SLP SLO SLM ISTAT MCK MDATA MLT RESET WDCK CLVI LOCK ASY EFM SPM
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