JVC-MXG65V-cs-sm维修电路原理图.pdf
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1、SERVICE MANUAL COMPACT COMPONENT SYSTEM ?No.20995 Jul. 2001 COPYRIGHT 2001 VICTOR COMPANY OF JAPAN, LTD. MX-G68V MX-G65V MX-G68V/MX-G65V Area Suffix USSingapore Safety precautions Preventing static electricity Important for laser products Disassembly method Wiring connection Adjustment method 1-2 1-
2、3 1-4 1-5 1-18? 1-19 Flow of functional operation until TOC read Maintenance of laser pickup Replacement of laser pickup Troubleshooting Description of major ICs 1-23 1-24 1-24 1-25 1-3352 Contents CA-MXG68V CA-MXG65V CANCEL /DEMO PRESET PLAY optional Programmable input/output 1 3.3V power supply 0V
3、 ground DRAM data bus DRAM data bus DRAM data bus DRAM data bus Column address strobe input to lach data from DRAM, rising edge active MX-G68V/MX-G65V 1-49 Pin No.Pin Name 27VDD5V 2834 MA 3738MA 41RAS# 42 DAEMP 43,60,69,92 VDD 45 PCMCLK 46PCMWS 47 PCMSD 48 EMP 49VSYNC# 50 HSYNC# 51CSYNC 5255PD 57VCL
4、K 5859PD 6162PDOPixel Data bus (2/2) Function 39CS# 7273SDI/O System data bus 76MCLK 77BUSY# 78ALE Main clock input, typically 40.5MHz I active HIGH, address latch enable for 8051 OBus BUSY, LOW indicates bus busy, open I 79SO OAddress select output, valid from IOAR+10h to IOAR+2fh (total 32 byteadd
5、resses), active LOW 80 IRQ#O active LOW Interrupt request output, active when an interrupt event is triggered, 81WR# 82RD# 8385SA I System address bus I Read enable, active LOW Iwrite enable, active LOW 86 VDD5V3.3V power supply 8791SA ISystem address bus 94 ACLK 95ACLKO IOptional secondary clock fo
6、r audio sampling rate, PCM clock OACLK output, ACLK and ACLKO are used for crystal input pins 96CDCLK 97 CDSD 98 CDWS 99 C2PO 100RESETISystem reset, active HIGH ICD bit clock input ICD serial data input I CD data word selector ICD data byte erasure flag type WE# I/O O O O O I O I/O O O O I/O O O O O
7、 Vertical synch, active LOW, input/output programmable, default in INPUT state Audio PCM clock output Audio PCM serial data output PCM channel word selector, active HIGH, programmable Audio emphasis flag, active HIGH DA emphasis input, active HIGH 3.3V power supply Row address strobe output, falling
8、 edge active Horizontal sync, active LOW, input/output programmable, default in INPUT state Composite sync signal, active LOW Pixel Data bus Pixel Data bus Video clock, usually 27MHz for TV scan, twice the luminance rate, input/output programmable, default in INPUT state Column address strobe output
9、, falling edge active 5V power supply DRAM address bus DRAM address bus Write enableoutput, active LOW to indicate write operation to DRAM 40 63 BLANK#OComposite blank, active LOW HSYNC# are in input state VSS 6568,70SD 0V ground I/OSystem data bus 64,71,75,93 KB9226 MX-G68V/MX-G65V 1-50 W9952QP (MI
10、C3) : TV encoder 2. Block diagram. 1. Pin layout FSADJ COMP VAA VREF_OUT VREF_IN NC CVBS_C AGND CVBS_Y AGND TEST HSYNCN VSYNCN VDD 5 6 7 8 9 10 11 12 13 4321323130 DGND W9952QP 14151617181920 26 25 24 23 22 21 27 28 29 SLEEP CBSWAP SVIDEO MASTER MODE3 MODE2 MODE1 MODE0 P7 P6 P5 P4 P3 P2 P1 P0 CLK DA
11、C Color Space Converter Video Timing Generator Sync/ Blank/ Pedestal MASTER CBSWAP SLEEP TESTVSYNCN HSYNCN C VREF _OUT COMP Y P7:0 VREF_IN FSADJ CLK Bandgap Voltage Reference DTO 8 Up Sampl- ing 8 MODE3:0 SVIDEO Modu - lator + 1.3 MHz Low Pass Filter Mux Mux DAC + MX-G68V/MX-G65V 1-51 3. Pin functio
12、n Pin No.SymbolI/O Function 21-28P7:0IYCrCb pixel inputs. They are latched on the falling edge of CLK. YCrCb input data conform to CCIR 601. 29CLKI2x Pixel clock input for 8-bit YCrCb data. 32VSYNCNI/OVertical sync input/output. VSYNCN is latched/output following the rising edge of CLK. 1HSYNCNI/OHo
13、rizontal sync input/output. HSYNCN is latched/output following the rising edge of CLK. 16MASTERIMaster/slave mode select. A logical high for master mode operation. A logical 0 for slave mode operation 15CBSWAPICr and Cb pixel sequence set up pin. A logic high swap the Cr and Cb sequence. 14SVIDEOISV
14、IDEO select input pin. A logic high selects Y/C output. A logic low selects composite video output. 13SLEEPIPower save mode. A logic high on this pin puts the chip into power-down mode. 17-20Mode3:0IMode configuration pin. 2TESTITest pin. These pins must be connected to DGND. 9VREF_INIVoltage refere
15、nce input. An external voltage reference must supply typical 1.235V to this pin. A 0.1uF ceramic capacitor must be used to decouple this input to GND. The decoupling capacitor must be as close as possible to minimize the length of the load. This pin may be connected directly to VREF_OUT. 8VREF_OUTOV
16、oltage reference output. It generates typical 1.2V voltage reference and may be used to drive VREF_IN pin directly. 5FSADJ-Full-Scale adjust control pin. The Full-Scale current of D/A converters can be adjusted by connecting a resistor (RSET) between this pin and ground. The relationship is 6COMP-Co
17、mpensation pin. A 0.1uF ceramic capacitor must be used to bypass this pin to VAA. The lead length must be kept as short as possible to avoid noise. 4CVBS_YOComposite/Luminance output. This is a high-impedance current source output. The output format can be selected by the PAL pin. The pin can drive
18、a 37.5 W load. If unused , this pin must be connected directly to GND. 11CVBS_COComposite/Chroma output. This is a high impedance current source Output. The output format can be selected by the PAL pin. The pin can drive a 37.5 W load. If unused, this pin must be connected directly to GND. 10NC-No c
19、onnection 31VDD-Digital power pin 30DGND-Digital ground pin 7VAA-Analog power pin 3,12AGND-Analog ground pin W9952QP MX-G68V/MX-G65V 1-52 W24257 (MIC2) : CMOS static RAM A4A3A2A1A0I/O2I/O1I/O3 VSS 1 32456 789 I/O4I/O5I/O6I/O8 I/O7A10OECSA11 232221201917181615 1011121314 282726 2524 A14 A12 A7A6A5 A9
20、A8A13WEVDD 2. Pin function Pin No. SymbolI/O Function 1A14 2 A12 3A7 4 A6 5 A5 6 A4 I I I I I I I 7 A3 8 A2 9 A1 I I I 10A0 Address input Address input Address input Address input Address input Address input Address input Data Input/Output Data Input/Output Data Input/Output Data Input/Output Data I
21、nput/Output Data Input/Output Chip select Input Data Input/Output Data Input/Output Data Input/Output Address input Address input Address input 11 I/O1I/O I/O I/O I/O I/O I/O I/O I/O 12 I/O2 13 I/O3 14 VSS 15 I/O4 16 I/O5 17 I/O6 18 I/O7 19 I/O8 20 CSI 21 A10I I 22OE OOut put enable 23 A11 24 25 26
22、27 28 A9 A8 A13 VDD WE I Address input Address input Address input Address input Write Enable input Power Supply Ground I I II I 1. Pin layout CSOEWE HXX LHH LHH LLH L XL 3. Truth table MX-G68V/MX-G65V 1-53 200107(V) VICTOR COMPANY OF JAPAN, LIMITED PERSONAL & MOBILE NETWORK BUSINESS UNIT. 10-1,1cho
23、me,Ohwatari-machi,Maebashi-city,371-8543,Japan (No.20995) MX-G68V/MX-G65V MX-G68V/MX-G65V ABCDEFG 1 2 3 4 5 2-1 Block diagram 1 2 KA9259 KB9226 KS9290 AIC3 AMP 4558 AUDIO OUT M66Q587 W9923 Video CD block Only U version FIC4/ HIC1/ JIC2 BA4560 MICON LC86654V-5V32 TO TUNER (RDS) SOURCE SELECTOR & E. V
24、OL TDA7442D FIC1 4CH D KA9258D RF ANAL SSP KB9226 DSP 5L9290 KA3082 KA3082 MX-G68V/MX-G65V HABCDEFG 1 2 3 4 5 2-2 MX-G68V/MX-G65V CD signal TAPE P.B. signal MAIN signal TUNER signal Main section SHEET 1/6 MIC signal TAPE REC signal Standard schematic diagrams SHEET 3/6 SHEET 6/6 SHEET 4/6 SHEET 2/5
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