Denon-AVR5805-avr-sm维修电路原理图.pdf

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1、SERVICE MANUAL AV SURROUND RECEIVER MODELAVR-5805 For U.S.A. otherwise, this pin is a CMOS output. 60 AVR-5805/AVC-A1XV DM1000 (IC201) 1394 P.W.B. 74 65 66 67 68 69 70 71 72 73 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 48 39 40 41 42 43 44 45 46 47 49 50

2、51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 DM1000 IEEE1394 a/b Interface Processor 128-pin QFP SWMATRIX6 *) SWMATRIX5 *) SWMATRIX4 *) SWMATRIX3 *) AV2CLK AV2CTRL1 / NCS2 VSSIO AV2CTRL0 / A20 VDDIO

3、 AV2DATA7 VSS AV2DATA6 VDD AV2DATA5 AV2DATA4 AV2DATA3 AV2DATA2 AV2DATA1 AV2DATA0 AV1CLK AV1CTRL1 AV1CTRL0 VSS VDD AV1DATA7 VDDIO AV1DATA6 VSSIO AV1DATA5 AV1DATA4 AV1DATA3 AV1DATA2 AV1DATA1 AV1DATA0 NTEST1 NRESET TEST2 PINT NWE NOE NCS0 VSS NCS1 VDD A10 A11 VSSIO VDDIO A12 VSS A13 VDD A14 A15 A16 A17

4、 *) SWMATRIX0 *) SWMATRIX1 *) SWMATRIX2 VSS EXTCLK VDD VCOIN VSSIO PDOUT VDDIO *) SWMATRIX8 *) SWMATRIX7 113 104 105 106 107 108 109 110 111 112 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 103 A0 A1 VSSIO VDDIO A2 A3 A4 A5 A6 A7 A8 A9 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 VSS

5、 D11 VDD D12 VDDIO VSSIO PHYCLK VSS PHYD7 VDD PHYD6 PHYD5 PHYD4 VSSIO PHYD3 VDDIO PHYD2 PHYD1 VSS PHYD0 VDD TEST3 LINKCLK VSSIO CTRL1 CTRL0 LREQ VDDIO VDDIO LPS VSSIO LINKON A18 A19 *) refer to chapter 4 fo r the Switch-Matrix descrip tion Pin Assignment by Pin Number PinNam ePinNam ePinNam ePinNam

6、e 1SWMATRIX6 *)33AV1DATA165D097A4 2SWMATRIX5 *)34AV1DATA766D198A5 3SWMATRIX4 *)35NTEST167D299A6 4SWMATRIX3 *)36NRESET68D3100A7 5AV2CLK37TEST269D4101A8 6AV2CTRL1 / NCS238PINT70D5102A9 7VSSIO39VDDIO71D6103A10 8AV2CTRL0 / A2040LPS72D7104A11 9VDDIO41VSSIO73D8105VSSIO 10AV2DATA742LINKON74D9106VDDIO 11VSS

7、43PHYCLK75D10107A12 12AV2DATA644VSS76VSS108VSS 13VDD45PHYD777D11109A13 14AV2DATA546VDD78VDD110VDD 15AV2DATA447PHYD679D12111A14 16AV2DATA348PHYD580VDDIO112A15 17AV2DATA249PHYD481VSSIO113A16 18AV2DATA150VSSIO82D13114A17 19AV2DATA051PHYD383D14115A18 20AV1CLK52VDDIO84D15116A19 21AV1CTRL153PHYD285NWE117S

8、WMATRIX0 *) 22VSS54PHYD186NOE118VSS 23AV1CTRL055VSS87NCS0119EXTCLK 24VDD56PHYD088VSS120VDD 25AV1DATA757VDD89NCS1121VCOIN 26VDDIO58TEST390VDD122VSSIO 27AV1DATA659LINKCLK91A0123PDOUT 28VSSIO60VSSIO92A1124VDDIO 29AV1DATA561CTRL193VSSIO125SWMATRIX1 *) 30AV1DATA462CTRL094VDDIO126SWMATRIX2 *) 31AV1DATA363

9、LREQ95A2127SWMATRIX8 *) 32AV1DATA264VDDIO96A3128SWMATRIX7 *) 61 AVR-5805/AVC-A1XV TC74VHC14FT (IC104,114) AD P.W.B. SN65LVDS1DBVR (IC108) D.VIDEO P.W.B. (IC102) AD P.W.B. (IC402) DIGITAL P.W.B. TC74VHC08FT (IC111) DIGITAL P.W.B. (IC319,321) AD P.W.B. TC74VHC244FT (IC112,304-307,403,406,408,603,906)

10、DIGITAL P.W.B. 3 2 4 5 (TOP VIEW) 1 VCC GND Z D Y 62 AVR-5805/AVC-A1XV TC74VHC04FT (IC113) DIGITAL P.W.B. TC4051BFT (IC121-123,125-127,129-131) A.VIDEO P.W.B. TC4052BFT (IC116-119,810,811) A.VIDEO P.W.B. TC4051BFT (IC112-115,124,128,132) A.VIDEO P.W.B. TC7SZ125F (IC308) DIGITAL P.W.B. TC74VHCT08AFT

11、(IC306) D.VIDEO P.W.B. KIA7912F-RTF (IC303,508) DIGITAL P.W.B. 123 1. GND 2. INPUT 3. OUTPUT 63 AVR-5805/AVC-A1XV TC9274F-022 (IC120,213,214,401,402) AUDIO P.W.B. TPS6734IDR (IC301) DIGITAL P.W.B. 1 2 3 4 8 7 6 5 EN REF SS COMP VCC FB OUT GND functional block diagram EN 1 EN 7 EN FB _ + 4 COMP Volta

12、ge Reference x3.5 SS Clamp Error AmplifierPWM Comparator R S 170-kHz Oscillator VCC Power Switch Drive Latch 2 REF 3 SS x6 Current Sense Amplifier Overcurrent Comparator Driver VCC OUT GND 8 6 5 + 1 M Q Terminal Functions TERMINAL DESCRIPTION NAMENO. DESCRIPTION EN1Enable. EN 2 V turns on the TPS673

13、4. EN 0.4 V turns it off and reduces the supply current to 3 A max. REF21.22-V reference voltage output. REF can source 100 A for external loads. SS3Soft Start. A capacitor between SS and GND brings the output voltage up slowly at power-up. COMP4Compensation connection. A 0.001-F capacitor between C

14、OMP and FB stabilizes the feedback loop. GND5Ground OUT6N-channel MOSFET drain connection FB7Feedback voltage. FB is connected to the converter output for the feedback loop. VCC8Supply voltage input 64 AVR-5805/AVC-A1XV AN13310BA (IC406) D.VIDEO P.W.B. AN13310BA Terminal Function 65 AVR-5805/AVC-A1X

15、V TC74LVX4051FT (IC401,408) 1394 P.W.B. SN65LVDS050PWR(IC401) DIGITAL P.W.B. (IC908) D.VIDEO P.W.B. LMC6772AIM (IC403) 1394 P.W.B. TC74VHCT244AFT (IC405,407) DIGITAL P.W.B. (IC907) D.VIDEO P.W.B. 2D 1D 1Y 1Z 2Y 2Z DE 9 15 12 14 13 10 11 2R 1R 1A 1B 2A 2B RE 5 3 4 2 1 6 7 1 2 3 4 5 6 7 8 16 15 14 13

16、12 11 10 9 1B 1A 1R RE 2R 2A 2B GND VCC 1D 1Y 1Z DE 2Z 2Y 2D (TOP VIEW) 66 AVR-5805/AVC-A1XV MN673747HL (IC410) D.VIDEO P.W.B. MN673747HL Terminal Function No.SymbolI/OFunction 1FIELD O Field discrimination signal output terminal 2VDD3 -3.3V 3VSS -GND 4APCE O Phase error 2fsc output terminal 5GCP O

17、Clamp Plus output (Sync-Tip) 6DAOUT O DAC data output terminal 7DAFLG O DAC select control terminal 8VDD -1.5V 9VDD3 -3.3V 10YIN0 I Y/CPS ADC input terminal (LSB) 11YIN1 I Y/CPS ADC input terminal 12YIN2 I Y/CPS ADC input terminal 13YIN3 I Y/CPS ADC input terminal 14YIN4 I Y/CPS ADC input terminal (

18、MSB) 15VSS -GND 16VDD3 -3.3V 17CIN0 I C/Cr/Cb ADC input terminal (LSB） 18CIN1 I C/Cr/Cb ADC input terminal 19CIN2 I C/Cr/Cb ADC input terminal 20CIN3 I C/Cr/Cb ADC input terminal 21CIN4 I C/Cr/Cb ADC input terminal (MSB） 22VDD -1.5V 23N.C. -Non-Connect 24CLK54I I ADC clock input terminal 25VSS -GND

19、26CLK54O O ADC clock input terminal 27VDD3 -3.3V 28ADFLG I ADC control 29VBIH I VBI Input terminal(Data) 30VBIL I VBI Input terminal (Sync.) 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137

20、 136 135 134 133 CSYNC VSS CLK27I VDD R656IN0 R656IN1 R656IN2 R656IN3 R656IN4 R656IN5 R656IN6 R656IN7 VDD3 VSS CLK27O VSS R656OUT0 R656OUT1 R656OUT2 R656OUT3 VDD3 VSS N.C. R656OUT4 R656OUT5 R656OUT6 R656OUT7 VDD3 RST VSS CLK27XI CLK27XO VDD3 VDD M0AD0 M0AD1 VSS M0AD2 M0AD3 VDD3 VSS M0AD4 M0AD5 VSS 1

21、FIELDM0AD6132 2VDD3M0AD7131 3VSSVDD3130 4APCEM0AD8129 5GCPM0AD9128 6DAOUTVSS127 7DAFLGM0AP126 8VDDM0BA125 9VDD3VDD3124 10YIN0VDD123 11YIN1M0DT0122 12YIN2M0DT1121 13YIN3VSS120 14YIN4M0DT2119 15VSSM0DT3118 16VDD3VDD3117 17CIN0M0DT4116 18CIN1M0DT5115 19CIN2VSS114 20CIN3M0DT6113 21CIN4M0DT7112 22VDDN.C.

22、111 23N.C.VDD3110 24CLK54IVSS109 25VSSM0DT8108 26CLK54OM0DT9107 27VDD3VSS106 28ADFLGM0DT10105 29VBIHM0DT11104 30VBILVDD3103 31SDARSTM0DT12102 32SDAM0DT13101 33VSSVSS100 34MICOMSEL1M0DT1499 35MICOMSELM0DT1598 36MICOMMODVDD97 37MICOMRWWVDD396 38MICOMRWRSDRCLKIN95 39VDD3VSS94 40MCSALESDRCLK93 41M?RESDR

23、POWUP92 42M?WENBWVDD391 43MAD6M0WE90 44MAD5M0CAS89 VSS MAD4 MAD3 MAD2 MAD1 MAD0 VDD3 VDD MDA15 MDA14 MDA13 MDA12 VSS MDA11 MDA10 MDA9 MDA8 VDD3 VSS MDA7 MDA6 N.C. N.C. N.C. MDA5 MDA4 VSS MDA3 MDA2 MDA1 MDA0 AVSS TCPOUT AVDD MINTEST SCANEN TST2 TST1 TST0 VDD3 M0CS M0RAS VSS VDD 45 46 47 48 49 50 51 5

24、2 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 MN673747HLMN673747HL LQFP176-P-2424BLQFP176-P-2424B 67 AVR-5805/AVC-A1XV 31SDARST I I2C reset signal input terminal(Not used VSS) 32SDA I/O I2C data in/output terminal (Not used VSS) 33VSS -

25、GND 34MICOMSEL1 I com I/F select input terminal 35MICOMSEL I com I/F select input terminal 36MICOMMOD I com mode select input terminal 37MICOMRWW O com encroachingus(WRITE)synchronous signal output terminal 38MICOMRWR O com encroachingus(READ)synchronous signal output terminal 39VDD3 -3.3V 40MCSALE

26、I com I/F chip select input terminal 41MNRE I com I/F read input terminal 42MNWENBW I com I/F write input terminal 43MAD6 I com I/F data/address input terminal (MSB) 44MAD5 I com I/F data/address input terminal 45VSS -GND 46MAD4 I com I/F data/address input terminal 47MAD3 I com I/F data/address inp

27、ut terminal 48MAD2 I com I/F data/address input terminal 49MAD1 I com I/F data/address input terminal 50MAD0 I com I/F data/address input terminal (LSB) 51VDD3 -3.3V 52VDD -1.5V 53MDA15 I/O com I/F data/address in/output terminal(MSB) 54MDA14 I/O com I/F data/address in/output terminal 55MDA13 I/O c

28、om I/F data/address in/output terminal 56MDA12 I/O com I/F data/address in/output terminal 57VSS -GND 58MDA11 I/O com I/F data/address in/output terminal 59MDA10 I/O com I/F data/address in/output terminal 60MDA9 I/O com I/F data/address in/output terminal 61MDA8 I/O com I/F data/address in/output t

29、erminal 62VDD3 -3.3V 63VSS -GND 64MDA7 I/O com I/F data/address in/output terminal 65MDA6 I/O com I/F data/address in/output terminal 66N.C. -Non-Connect 67N.C. -Non-Connect 68N.C. -Non-Connect 69MDA5 I/O com I/F data/address in/output terminal 70MDA4 I/O com I/F data/address in/output terminal 71VS

30、S -GND 72MDA3 I/O com I/F data/address in/output terminal 73MDA2 I/O com I/F data/address in/output terminal 74MDA1 I/O com I/F data/address in/output terminal 75MDA0 I/O com I/F data/address in/output terminal (LSB) 76AVSS -PLL GND 77TCPOUT I/O PLL TEST(OPEN) 78AVDD -3.3V PLL 79MINTESTI Test (OPEN

31、or VSS) 80SCANEN I Test (OPEN or VSS) 81TST2 I Test (OPEN or VSS) 82TST1 I Test (OPEN or VSS) 83TST0 I Test (OPEN or VSS) 84VDD3 -3.3V 85M0CS O SDRAM CS output terminal 86M0RAS O SDRAM RAS output terminal 87VSS -GND 88VDD -1.5V 89M0CAS O SDRAM CAS output terminal 90M0WE O SDRAM WE output terminal 91

32、VDD3 -3.3V 92SDRPOWUP I Test (OPEN or VSS) 93SDRCLK O SDRAM clock output terminal SDRAM 94VSS -GND 95SDRCLKIN I SDRAM clock input terminal 96VDD3 -3.3V 97VDD -1.5V 98M0DT15 I/O SDRAM data in/output terminal(MSB) 99M0DT14 I/O SDRAM data in/output terminal 100VSS -GND 101M0DT13 I/O SDRAM data in/outpu

33、t terminal 102M0DT12 I/O SDRAM data in/output terminal 103VDD3 -3.3V 104M0DT11 I/O SDRAM data in/output terminal 105M0DT10 I/O SDRAM data in/output terminal 106VSS -GND 107M0DT9 I/O SDRAM data in/output terminal No.SymbolI/OFunction 68 AVR-5805/AVC-A1XV 108M0DT8 I/O SDRAM data in/output terminal 109

34、VSS -GND 110VDD3 -3.3V 111N.C. -Non-Connect 112M0DT7 I/O SDRAM data in/output terminal 113M0DT6 I/O SDRAM data in/output terminal 114VSS -GND 115M0DT5 I/O SDRAM data in/output terminal 116M0DT4 I/O SDRAM data in/output terminal 117VDD3 -3.3V 118M0DT3 I/O SDRAM data in/output terminal 119M0DT2 I/O SD

35、RAM data in/output terminal 120VSS -GND 121M0DT1 I/O SDRAM data in/output terminal 122M0DT0 I/O SDRAM data in/output terminal (LSB) 123VDD -1.5V 124VDD3 -3.3V 125M0BA O SDRAM address output terminal(MSB) 126M0AP O SDRAM address output terminal 127VSS -GND 128M0AD9 O SDRAM address output terminal 129

36、M0AD8 O SDRAM address output terminal 130VDD3 -3.3V 131M0AD7 O SDRAM address output terminal 132M0AD6 O SDRAM address output terminal 133VSS -GND 134M0AD5 O SDRAM address output terminal 135M0AD4 O SDRAM address output terminal 136VSS -GND 137VDD3 -3.3V 138M0AD3 O SDRAM address output terminal 139M0

37、AD2 O SDRAM address output terminal 140VSS -GND 141M0AD1 O SDRAM address output terminal 142M0AD0 O SDRAM address output terminal(LSB) 143VDD -1.5V 144VDD3 -3.3V 145CLK27XO - clock 27 MHz output terminal(Xtal) 146CLK27XI - clock 27 MHz input terminal(Xtal) 147VSS -GND 148RST I reset input terminal 1

38、49VDD3 -3.3V 150R656OUT7 O Rec.656 output terminal(MSB) 151R656OUT6 O Rec.656 output terminal 152R656OUT5 O Rec.656 output terminal 153R656OUT4 O Rec.656 output terminal 154N.C. -Non-Connect 155VSS -GND 156VDD3 -3.3V 157R656OUT3 O Rec.656 output terminal 158R656OUT2 O Rec.656 output terminal 159R656

39、OUT1 O Rec.656 output terminal 160R656OUT0 O Rec.656 output terminal(LSB) 161VSS -GND 162CLK27O O clock 27 MHz output terminal 163VSS -GND 164VDD3 -3.3V 165R656IN7 IRec.656 input terminal (MSB) (Not used Open or VSS) 166R656IN6 IRec.656 input terminal (Not used Open or VSS) 167R656IN5 IRec.656 input

40、 terminal (Not used Open or VSS) 168R656IN4 IRec.656 input terminal (Not used Open or VSS) 169R656IN3 IRec.656 input terminal (Not used Open or VSS) 170R656IN2 IRec.656 input terminal (Not used Open or VSS) 171R656IN1 IRec.656 input terminal (Not used Open or VSS) 172R656IN0 IRec.656 input terminal

41、(LSB) (Not used Open or VSS) 173VDD -1.5V 174CLK27I I Clock 27 MHz input terminal 175VSS -GND 176CSYNC I/O Composite Sync. in/output terminal No.SymbolI/OFunction 69 AVR-5805/AVC-A1XV M95128-WMN6T (IC410) DIGITAL P.W.B. TC74VCX04FT (IC411) D.VIDEO P.W.B. TC74VHC125FT (IC412,413) DIGITAL P.W.B. FCXO-

42、03L(27.000MHz) (IC412) D.VIDEO P.W.B. FCXO-03L(27.5792MHz) (IC420) 1394 P.W.B. DVSS C HOLDQ SVCC W AI01790D 1 2 3 4 8 7 6 5 VOUT STANDBYGND DD 70 AVR-5805/AVC-A1XV K4S161622H-TC60 (IC413) D.VIDEO P.W.B. VDD DQ0 DQ1 VSSQ DQ2 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ LDQM WE CAS RAS CS BA A10/AP A0 A1 A2 A3

43、VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 PIN CONFIGURATION(TOP VIEW) VSS DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ N.C/RFU UDQM CLK CKE N.C A9 A8 A7 A6 A5 A4 VSS 50PIN TSOP (II) (4

44、00mil x 825mil) (0.8 mm PIN PITCH) PIN FUNCTION DESCRIPTION PinNameInput Function CLKSystem ClockActive on the positive going edge to sample all inputs. CSChip Select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and L(U)DQM CKEClock Enable Masks system clock

45、 to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. A0 A10/APAddress Row / column addresses are multiplexed on the same pins. Row address : RA0 RA10, column address : CA0 CA7 BABank Select Add

46、ress Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RASRow Address Strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CASColumn Address Strobe Latches column addre

47、sses on the positive going edge of the CLK with CAS low. Enables column access. WEWrite Enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. L(U)DQMData Input/Output Mask Makes data output Hi-Z, tSHZafter the clock and masks the output. Blocks data input wh

48、en L(U)DQM active. DQ015Data Input/OutputData inputs/outputs are multiplexed on the same pins. VDD/VSSPower Supply/GroundPower and ground for the input buffers and the core logic. VDDQ/VSSQData Output Power/Ground Isolated power supply and ground for the output buffers to provide improved noise immu

49、nity. N.C/RFU No Connection/ Reserved for Future Use This pin is recommended to be left No Connection on the device. FUNCTIONAL BLOCK DIAGRAM * Samsung Electronics reserves the right to change products or specification without notice. Bank Select Data Input Register 512K x 16 512K x 16 Sense AMP Output BufferI/O Control Column Decoder Latency & Burst Length Progr