Denon-AVRX500-avr-sm维修电路原理图.pdf

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1、START:|qzT7t3cIXfGvpSN6RPbAWw=|CqN5zsKr96YP4BreAbdr2NqZwvosEWSgtpmHebiaRr4=|RtRIz5LbaS+BXuKmvA5tJg=|:END D supports TMDS logic level. 48 TXC+ HDMI Output Differential Clock Output. Differential clock output at the TMDS clock rate; supports TMDS logic level. 100 ADV7623 Hardware Manual Rev. 0 March 2

2、010 19 Confidential NDA required Location Mnemonic Type Description 49 TXGND Ground TXAVDD Ground 50 TX0- HDMI Output Differential Output Channel 0 Complement. Differential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 51 TX0+ HDMI Output Differential Output Channel 0

3、 True. Differential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 52 TXGND Ground TXAVDD Ground 53 TX1- HDMI Output Differential Output Channel 1 Complement. Differential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 54 TX1+ HDMI Output

4、 Differential Output Channel 1 True. Differential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 55 TXAVDD Power 1.8V power supply for TMDS outputs 56 TX2- HDMI Output Differential Output Channel 2 Complement. Differential output of the red data at 10 the pixel clock r

5、ate; supports TMDS logic level. 57 TX2+ HDMI Output Differential Output Channel 2 True. Differential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 58 TXGND Ground TXAVDD Ground 59 CEC Digital I/O Consumer electronic control channel. 60 DGND Ground Ground for DVDD 61 D

6、VDD Power Digital supply voltage (1.8 V) 62 ALSB Digital Input This pin is used to set I2C address of the Rx IO and the Tx Main Map. 63 CSB Digital Input Chip Select pin. This pin must be set low or left floating for the chip to process I2C messages that are destined to the ADV7623. The ADV7623 igno

7、res I2C messages which he receives if this pin is high. 64 EP_SCK Digital Output SPI clock interface for the EDID/OSD 65 EP_CS Digital Output SPI chip selected interface for the EDID/OSD 66 EP_MOSI Digital Output SPI master out/slave in for the EDID/OSD 67 EP_MISO Digital Input SPI master in/slave o

8、ut for the EDID/OSD 101 ADV7623 Hardware Manual Rev. 0 March 2010 20 Confidential NDA required Location Mnemonic Type Description 68 MCLK_IN Digital Input Audio Reference Clock. 128 N fs with N = 1, 2, 3, or 4. Set to 128 sampling frequency (fs), 256 fs, 384 fs, or 512 fs. Supports 1.8 V to 3.3 V CM

9、OS logic levels. 69 SCLK_IN Digital Input I2S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V. 70 AP5_IN Digital Input Audio Input Port 5. CMOS logic levels from 1.8 V to 3.3 V. 71 AP4_IN Digital Input Audio Input Port 4. CMOS logic levels from 1.8 V to 3.3 V. 72 DGNDIO Ground Ground for

10、 DVDDIO 73 DVDDIO Power Digital I/O supply voltage (3.3 V) 74 AP3_IN Digital Input Audio Input Port 3. CMOS logic levels from 1.8 V to 3.3 V. 75 AP2_IN Digital Input Audio Input Port 2. CMOS logic levels from 1.8 V to 3.3 V. 76 AP1_IN Digital Input Audio Input Port 1. CMOS logic levels from 1.8 V to

11、 3.3 V. 77 AP0_IN Digital Input Audio Input Port 0. CMOS logic levels from 1.8 V to 3.3 V. 78 SDATA Digital I/O I2C port serial data input/output pin. SDA is the data line for the control port. 79 SCL Digital Input I2C port serial clock input. SCL is the clock line for the control port. 80 DGND Grou

12、nd Ground for DVDD 81 DVDD Power Digital supply voltage (1.8 V) 82 INT1 (AMUTE1) Digital Output Interrupt pin, can be active low or active high. When status bits change, this pin is triggered. The events that trigger an interrupt are under user control. This pin can also output an audio mute signal

13、83 INT2 (AMUTE2) Digital Output Interrupt pin, can be active low or active high. When status bits change, this pin is triggered. The events that trigger an interrupt are under user control. This pin can also output an audio mute signal. I2C LSB selection. 84 INT_TX Digital Output Interrupt. Open dra

14、in. A 2 k pull-up resistor to the microcontroller I/O supply is recommended. 85 DGNDIO Ground Ground for DVDDIO 86 DVDDIO Power Digital I/O supply voltage (3.3 V) 102 ADV7623 Hardware Manual Rev. 0 March 2010 21 Confidential NDA required Location Mnemonic Type Description 87 AP0_OUT Digital Output A

15、udio output port 0. 88 AP1_OUT Digital Output Audio output port 1. 89 AP2_OUT Digital Output Audio output port 2. 90 AP3_OUT Digital Output Audio output port 3. 91 AP4_OUT Digital Output Audio output port 4. 92 DGND Ground Ground for DVDD 93 DVDD Power Digital supply voltage (1.8 V) 94 AP5_OUT Digit

16、al Output Audio output port 5. 95 SCLK_OUT Digital Output Audio serial clock output. 96 MCLK_OUT Digital Output Audio master clock output. 97 RESETB Digital Input System reset input. Active low. A minimum low reset pulse width of 5 ms is required to reset the ADV7623 circuitry. 98 PWRDNB Digital Inp

17、ut Active low power-down pin. This pin should be used as a system power detect when the internal EDID is powered from the 5V signal from the HDMI port when connected to active equipment. Pin pulled down internally. 99 PGND Ground Ground for PVDD 100 PVDD Power PLL supply voltage 101 XTAL Miscellaneo

18、us Analog Input pin for 28.63636 MHz crystal or an external 1.8 V 28.63636 MHz clock oscillator source to clock the ADV7623. The following crystal frequencies are also supported: 24.576 MHz and 27 MHz. 102 XTAL1 Miscellaneous Analog Crystal output pin. This pin should be left floating if a clock osc

19、illator is used. 103 PVDD Power PLL supply voltage 104 PGND Ground PVDD Ground 105 HP_CTRLA Digital Output Hot Plug Detect for port A. 106 5V_DETA Digital Input 5 V detect pin for port A in the HDMI interface. 107 RTERM Miscellaneous Analog Sets internal termination resistance. A 500 resistor betwee

20、n this pin and GND should be used. 108 DDCA_SDA Digital I/O HDCP slave serial data port A. DDCD_SDA is a 3.3 V input/output that is 5 V tolerant. 109 DDCA_SCL Digital Input HDCP slave serial clock port A. DDCD_SCL is a 3.3 V input that is 5 V tolerant. 110 CVDD Power Receiver comparator supply volta

21、ge (1.8V) 103 ADV7623 Hardware Manual Rev. 0 March 2010 22 Confidential NDA required Location Mnemonic Type Description 111 CGND Ground TVDD and CVDD Ground 112 RXA_C- HDMI Input Digital input clock Complement of port A in the HDMI interface. 113 RXA_C+ HDMI Input Digital input clock True of port A

22、in the HDMI interface. 114 TVDD Power Receiver terminator supply voltage (3.3 V) 115 RXA_0- HDMI Input Digital input channel 0 complement of port A in the HDMI interface. 116 RXA_0+ HDMI Input Digital input channel 0 true of port A in the HDMI interface. 117 CGND Ground TVDD and CVDD Ground 118 RXA_

23、1- HDMI Input Digital input channel 1 complement of port A in the HDMI interface. 119 RXA_1+ HDMI Input Digital input channel 1 true of port A in the HDMI interface. 120 TVDD Power Receiver terminator supply voltage (3.3 V) 121 RXA_2- HDMI Input Digital input channel 2 complement of port A in the HD

24、MI interface. 122 RXA_2+ HDMI Input Digital input channel 2 true of port A in the HDMI interface. 123 HP_CTRLB Digital Output Hot Plug Detect for port B. 124 5V_DETB Digital Input 5 V detect pin for port B in the HDMI interface. 125 DGND Ground Ground for DVDD 126 DVDD Power Digital supply voltage (

25、1.8 V) 127 DDCB_SDA Digital I/O HDCP slave serial data ports B. DDCB_SDA is a 3.3 V input/output that is 5 V tolerant. 128 DDCB_SCL Digital Input HDCP slave serial clock port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant. 129 CVDD Power Receiver comparator supply voltage (1.8V) 130 CGND Ground T

26、VDD and CVDD Ground 131 RXB_C- HDMI Input Digital input clock complement of port B in the HDMI interface. 132 RXB_C+ HDMI Input Digital input clock true of port B in the HDMI interface. 133 TVDD Power Receiver terminator supply voltage (3.3 V) 134 RXB_0- HDMI Input Digital input channel 0 complement

27、 of port B in the HDMI interface. 135 RXB_0+ HDMI Input Digital input channel 0 true of port B in the HDMI interface. 136 CGND Ground TVDD and CVDD Ground 137 RXB_1- HDMI Input Digital input channel 1 complement of port 104 MX25L8006EM2I-12G (DIGITAL : IC14, IC82) ADV7623 Hardware Manual Rev. 0 Marc

28、h 2010 23 Confidential NDA required Location Mnemonic Type Description B in the HDMI interface. 138 RXB_1+ HDMI Input Digital input channel 1 true of port B in the HDMI interface. 139 TVDD Power Receiver terminator supply voltage (3.3 V) 140 RXB_2- HDMI Input Digital input channel 2 complement of po

29、rt B in the HDMI interface. 141 RXB_2+ HDMI Input Digital input channel 2 true of port B in the HDMI interface. 142 HP_CTRLC Digital Output Hot Plug Detect for port C. 143 5V_DETC Digital Input 5 V detect pin for port C in the HDMI interface. 144 DDCC_SDA Digital I/O HDCP slave serial clock port C.

30、DDCC_SDA is a 3.3 V input/output that is 5 V tolerant. CS#1 2 3 4 8 7 6 5 SO/SIO1 WP# GND VCC HOLD# SCLK SI/SIO0 SYMBOL CS# SI/SIO0 SO/SIO1 SCLK WP# HOLD# VCC GND Chip Select Serial Data Input (for 1 x I/O)/ Serial Data Input & Output (for Dual Output mode) Serial Data Output (for 1 x I/O)/ Serial D

31、ata Output (for Dual Output mode) Clock Input Write protection + 3.3V Power Supply Ground Hold, to pause the device without deselecting the device DESCRIPTION PIN DESCRIPTION 105 AD8195 (F-HDMI : IC51) AD8195 Terminal Functions NOTES 1. THE AD8195 LFCSP HAS AN EXPOSED PAD ON THE UNDERSIDE OF THE PAC

32、KAGE THAT AIDS IN HEAT DISSIPATION. THE PAD MUST BE ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE IN ORDER TO MEET THERMAL SPECIFICATIONS. AD8195 TOP VIEW (Not to Scale) 1IN0 2IP0 3IN1 4IP1 5VTTI 6IN2 7IP2 10AVCC 30 AVCC 29 PE_EN 28 TX_EN 27 AVEE 26 AVCC 25 AVCC 24 AVEE 21 COMP 40 SCL_IN 39 SDA_IN

33、 38 CEC_IN 37 AVEE 36 VREF_IN 35 SCL_OUT 34 SDA_OUT 31 CEC_OUT 11ON0 12OP0 13VTTO 14ON1 15OP1 16AVCC 17ON2 20OP3 9IP3 8IN3 22 AVCC 23 AVCC 19ON3 18OP2 32 AMUXVCC 33 VREF_OUT PIN 1 INDICATOR Mnemonic IN0 IP0 IN1 IP1 VTTI IN2 IP2 IN3 IP3 AVCC ON0 OP0 VTTO ON1 OP1 ON2 OP2 ON3 OP3 COMP AVEE TX_EN PE_EN

34、CEC_OUT AMUXVCC VREF_OUT SDA_OUT SCL_OUT VREF_IN CEC_IN SDA_IN SCL_IN Type1 HS I HS I HS I HS I Power HS I HS I HS I HS I Power HS O HS O Power HS O HS O HS O HS O HS O HS O Control Power Control Control LS I/O Power Reference LS I/O LS I/O Reference LS I/O LS I/O LS I/O Description High Speed Input

35、 Complement. High Speed Input. High Speed Input Complement. High Speed Input. Input Termination Supply. Nominally connected to AVCC. High Speed Input Complement. High Speed Input. High Speed Input Complement. High Speed Input. Positive Analog Supply. 3.3 V nominal. High Speed Output Complement. High

36、 Speed Output. Output Termination Supply. Nominally connected to AVCC. High Speed Output Complement. High Speed Output. High Speed Output Complement. High Speed Output. High Speed Output Complement. High Speed Output. Power-On Compensation Pin. Bypass to ground through a 10 F capacitor. Negative Ana

37、log Supply. 0 V nominal. High Speed Output Enable Parallel Interface. High Speed Preemphasis Enable Parallel Interface. CEC Output Side. Positive Auxiliary Buffer Supply. 5 V nominal. DDC Output Side Pull-Up Reference Voltage. DDC Output Side Data Line Input/Output. DDC Output Side Clock Line Input/

38、Output. DDC Input Side Pull-Up Reference Voltage. CEC Input Side. DDC Input Side Data Line. DDC Input Side Clock Line Pin No. 1 2 3 4 5 6 7 8 9 10, 16, 22, 23, 25, 26, 30 11 12 13 14 15 17 18 19 20 21 24, 27, 37, Exposed Pad 28 29 31 32 33 34 35 36 38 39 40 1 HS = high speed, LS = low speed, I = inp

39、ut, and O = output. 106 EN5339QI (DIGITAL : IC17) EX3AV Terminal Functions 06903March 30, 2012Rev: A EN5339QI Enpirion 2012 all rights reserved, E&OE , Page 2 Part Number Package Markings Temp Rating ( C) Package Description EN5339QI EN5339 -40 to +85 24-pin (4mm x 6mm x 1.1mm) QFN T&R EN5339QI-E EN

40、5339 QFN Evaluation Board Packing and Marking Information: Figure 3: Pin Out Diagram (Top View) NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in

41、part malfunction or damage. NOTE B: Grey area highlights exposed metal on the bottom of the package that is not to be mechanically or electrically connected to the PCB. There should be no traces on PCB top layer under these keep out areas. NOTE C: White dot on top left is pin 1 indicator on top of t

42、he device package. PIN NAME FUNCTION 1, 21-24 NC(SW) NO CONNECT: These pins are internally connected to the common switching node of the internal MOSFETs. They must be soldered to PCB but not be electrically connected to any external signal, ground, or voltage. Failure to follow this guideline may r

43、esult in device damage. 2-3, 8-9 PGND Input and output power ground. Connect these pins to the ground electrode of the input and output filter capacitors. See VOUT, PVIN descriptions and Layout Recommendation for more details. 4-7 VOUT Regulated converter output. Connect to the load and place output

44、 filter capacitor(s) between these pins and PGND pins 7 and 8. See layout recommendation for details 10 TST2 Test Pin. For Enpirion internal use only. Connect to AVIN at all times. 11 TST1 Test Pin. For Enpirion internal use only. Connect to AVIN at all times. 06903March 30, 2012Rev: A EN5339QI Enpi

45、rion 2012 all rights reserved, E&OE , Page 2 PIN NAME FUNCTION 1, 21-24 NC(SW) NO CONNECT: These pins are internally connected to the common switching node of the internal MOSFETs. They must be soldered to PCB but not be electrically connected to any external signal, ground, or voltage. Failure to f

46、ollow this guideline may result in device damage. 2-3, 8-9 PGND Input and output power ground. Connect these pins to the ground electrode of the input and output filter capacitors. See VOUT, PVIN descriptions and Layout Recommendation for more details. 4-7 VOUT Regulated converter output. Connect to

47、 the load and place output filter capacitor(s) between these pins and PGND pins 7 and 8. See layout recommendation for details 10 TST2 Test Pin. For Enpirion internal use only. Connect to AVIN at all times. 11 TST1 Test Pin. For Enpirion internal use only. Connect to AVIN at all times. 06903March 30

48、, 2012Rev: A EN5339QI Enpirion 2012 all rights reserved, E&OE , Page 3 PIN NAME FUNCTION 12 TST0 Test Pin. For Enpirion internal use only. Connect to AVIN at all times. 13 NC NO CONNECT: This pin must be soldered to PCB but not electrically connected to any other pin or to any external signal, volta

49、ge, or ground. This pin may be connected internally. Failure to follow this guideline may result in device damage. 14 VFB This is the external feedback input pin. A resistor divider connects from the output to AGND. The mid-point of the resistor divider is connected to VFB. A feed-forward capacitor is required parallel to the upper feedback resistor (RA). The output voltage regulation is based on the VFB node voltage equal to 0.600V. 15 AGND The quiet ground for the cont