Denon-AVR3805EU-avr-sm维修电路原理图.pdf
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1、SERVICE MANUAL MODEL AVR-3805 AVC-3890 AV SURROUND RECEIVER / AMPLIFIER 16-11, YUSHIMA 3-CHOME, BUNKYO-KU, TOKYO 113-0034 JAPAN X0197V.02 DE/CDM 0403 For Europe Edge detection is “Ed”; Detection by both shifting is “E Serial data detection is “S” (Serial data output is also “S”). Res: State at reset
2、. “H”= Outputs High Level at reset “L”= Outputs Low Level at reset “Z”= Becomes High impedance mode at reset STBY: State of port when STANDBY mode. “O/L” = Output port and “L” “I”= Input port Stop: State of port when Stop mode. “O/L”= Output port and “L” “I”= Input port 32 32AVR-3805 / AVC-3890 LC89
3、057W Terminal Function Function Pin No. Pin Name LC89057W (AD: IC814, 815, 816) 1RXOUTOInput bi-phase select data output terminal 2RX0ITTL compatible digital data input terminal 3RX1ICoaxial compatible amp built-in digital data input terminal 4RX2ITTL compatible digital data input terminal 5RX3ITTL
4、compatible digital data input terminal 6DGNDDigital GND 7DVDDDigital power 8RX4ITTL compatible digital data input terminal 9RX5/VIITTL compatible digital data/Validity flag input terminal for modulation 10RX6/UIITTL compatible digital data/User data input terminal for modulation 11DVDDDigital power
5、for PLL 12DGNDDigital GND for PLL 13LPFOPLL loop filter connecting terminal 14AVDDAnalog power for PLL 15AGNDAnalog GND for PLL 16RMCKORMCK clock output terminal (256fs, 512fs, XIN, VCO) 17RBCKO/IRBCK clock in/output terminal (64fs) 18DGNDDigital GND 19DVDDDigital power 20RLRCKO/IRLRCK clock in/outp
6、ut terminal (fs) 21RDATAOSerial audio data output terminal 22SBCKOSBCK clock output terminal (32fs, 64fs, 128fs) 23SLRCKOSLRCK clock output terminal (fs/2, fs, 2fs) 24SDINISerial audio data input terminal 25DGNDDigital GND 26DVDDDigital power 27XMCKOOsc. amp output terminal I/O 36 RERR1RXOUT 35 INT2
7、RX0 34 CKST3RX1 33 AUDIO/VO4RX2 32 EMPHA/UO5RX3 31 DGND6DGND 30 DVDD7DVDD 29 XIN8RX4 28 XOUT9RX5/VI 27 XMCK10RX6/UI 26 DVDD11DVDD 25 DGND12DGND 24SDIN37DO 23SLRCK38DI 22SBCK39CE 21RDATA40CL 20RLRCK41XMODE 19DVDD42DGND 18DGND43DVDD 17RBCK44TMCK/PIO0 16RMCK45TBCK/PIO1 15AGND46TLRCK/PIO2 14AVDD47TDATA/
8、PIO3 13LPF48TXO/PIOEN TOP VIEW 1RXOUT 32 EMPHA/UO 33 AUDIO/VO 35 INT 40 CL 39 CE 38 DI 28 XOUT 29 XIN 27 XMCK 34 CKST 41 XMODE Input Selector 2RX0 3RX1 4RX2 5RX3 8RX4 9RX5/VI 10RX6/UI 37DO 36RERR 21RDATA 24SDIN 16RMCK 17RBCK 20RLRCK 22SBCK 23SLRCK 13LPF 44TMCK/PIO0 45TBCK/PIO1 46TLRCK/PIO2 47TDATA/P
9、IO3 48TXO/PIOEN Clock Selector C bit, U bit PLL Demodulation 128fs, 256fs, 384fs, 512fs or 768fs. * 19RSTIReset, power down input, active LOW. * 20OVFROOverflow signal of R-channel in PCM mode. This is available in PCM mode only. 21OVFLOOverflow signal of L-channel in PCM mode. This is available in
10、PCM mode only. 22VCCAnalog power supply. 23AGNDAnalog ground. 24VINRIR-channel analog input, negative pin. 25VINR+IR-channel analog input, positive pin. 26VCOMRR-channel analog common mode output. 27AGNDRAnalog ground for VREFR. 28VREFRR-channel voltage reference output, requires capacitors for deco
11、upling to AGND. I/O * Schmitt trigger input with internal pull-down (51kohm typically), 5V tolerant. * Schmitt trigger input, 5V tolerant. * Schmitt trigger input. 37 37AVR-3805 / AVC-3890 LC75721E (VI: IC701, 702) TA1270BF (VI: IC111)TA8772AN (VI: IC501) Except U.S.A., Canada 1IN/LOW; 2IN) 31 R-Y1
12、INPUT 30 B-Y1 INPUT 29 Y1 INPUT 28 I2C GND 27 R-Y2 INPUT 26 B-Y2 INPUT 25 Y2 INPUT 24 23 22 21 20 19 18 17 16 15 SW GND ADRS SW R-Y/R OUTPUT B-Y/B OUTPUT Y/G OUTPUT SW Vcc (9V) SYNC Vcc (9V) CP/HP INPUT Dig GND SCP OUTPUT DAC2 DAC1 fsc Y DL Y DL SW SW PEDESTAL CLAMP 1H DL CONTROL SECAM CONTROL CbCr
13、/ UV SW fsc TRAP OFFSET SW LPF / fsc TRAP BPFH. AFCH C / D 32fH VCO V C / D ACC TOF SCP SW APC P / N ID SYSTEM CW MATRIX TINT DEMO CHROMA BLK NOSE DET YUV RGB MATRIX CP / HP IN SW V SEP SYNC SEP SUB-COLOR VCXO SUB- CONTRAST Y OFFSET SW DAC TEST Ys I2C BUS CONTROL PEDESTAL CLAMP PEDESTAL CLAMP HI: 20
14、h/LOW: 24h 1 BIASVB1 2 VRT 27 COUT 3 VDD1 26 VSS1 4 TESTI1 25 YOUT 5 VSS2 24 VB2 6 VRB 23 PD 7 YCIN 22 FIL 8 TEST 21 VSS4 9 KILLER 20 VDD4 10 TESTI2 19 FSC 11 VDD3 18 TESTOUT 12 VSS3 17 MODE1 13 VDD2 16 SDA 14 TESTI3 15 SCL CORING PEAKING DAC 1/8 (8fsc) 8fsc4fsc DAC IIC BUS 28 PLL DET1/2VCO Ped. CLI
15、P LPFDELAY CNR C-N.C CORING V-ENHANCER KILLER DYNAMIC COMB FILTER Sync. Clamp ADC LINE MEMORY LINE MEMORY INTERPOLATION 302928272625242322212019181716 123456789101112131415 2 1 1 or Pulse Elimination Pulse Elimination 2 1 1 or Pulse Insertion Pulse Insertion AGC Detector AGC Detector Detector ClampC
16、lamp Clamp Clamp AGCAGC LPFLPF Pulse HG. GP 225fH VCO 1/225 Clock Average Bias CCD 1HCCD 1H Bipolar Circuit CCD Circuit S / HS / H REFREF + + 38 38AVR-3805 / AVC-3890 MM74HC4053SJ (CV: IC451) 1 2 VEE 3 4 5 6 7 89 10 11 16 15 14 13 12 Y1 Y0 Z1 Z Z0 Enable GND Vcc Y X1 X X0 C A B X = Dont Care Truth T
17、able Control Inputs Select Enable C B A ONSwitches L L L L Z0 Y0 X0 L L L H Z0 Y0 X1 L L H L Z0 Y1 X0 L L H H Z0 Y1 X1 L H L L Z1 Y0 X0 L H L H Z1 Y0 X1 L H H L Z1 Y1 X0 L H H H Z1 Y1 X1 H X X X None SN74HC151APW (AD: IC806, 807) Data Inputs Outputs GND Strobe 3 2 1 0 Y W 1 2 3 4 5 6 7 8 D2 D1 D0 Y
18、W S D5 D6 D7 A D4 B C 16 15 14 13 12 11 10 9 Vcc 5 6 7 A B C 4 Data Inputs Data Select 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1A 1B 1Y 2A 2B 2Y GND Vcc 4B 4Y 4A 3B 3A 3Y BU4051BCF SN74AHCT08NS(CV:IC703) (CV: IC251, 252, 504507) SN74LV08APW(AD:IC822) Channel IN/OUT X4 X6 X X7 X5 INHIBIT VEE Vss VDD X2 X1 X
19、0 X3 A B C Common Channel IN/OUT OUT/IN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4 C 6 OUT/IN 7 5 INH VEE 2 1 0 3 A B BU4053BCF (VI: IC101) (CV: IC256) Y1 Y0 Z1 Z Z0 INH VEE Vss VDD Y X X1 X0 A B C 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 C Y X X1 X0 A B Y0 Z1 Z Z0 INH VEE Y1 TC9459F (AD: IC381) Except
20、Japan model BU4052BCF (VI: IC105, IC108) (CV: IC255, 509, 510) (CO:IC507) Y0 Y2 COMMON Y Y3 Y1 INH VEE Vss VDD X2 X1 COMMON X X0 X3 A B 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 B X2 X1 XOUT /IN X0 X3 A Y2 YOUT /IN Y3 Y1 INH VEE Y0 L-LD2 8 L-ch7 to 91decoder R-ch latch circuit R-ch7 to 91decoder 9 16 1
21、9 3 2 4 5 6 7 10 11 12 24 22 23 21 20 18 17 15 14 13 1 NC L-OUT L-IN L-LD1 L-A-GND NC NC GND CK VSSVDD NC R-OUT R-LD1 R-LD2 R-A-GND NC CS2 NC STB DATA R-IN 50kohm/ 91STEP VR Same as L-ch L-ch latch circuit Shift register (24Bit) Level shift circuit CS1 1 2 3 4 5 6 7 8 10 9 20 19 18 17 16 15 14 13 12
22、 11 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND Vcc 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 TOP VIEW SN74LV573APW (DS: IC302, 303) 1 2 3 4 5 6 7 8 10 9 20 19 18 17 16 15 14 13 12 11 OE D0 D1 D2 D3 D4 D5 D6 D7 GND Vcc Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 LE D Q L D Q L D Q L D Q L D Q L D Q L D Q L D Q L D0D1D2D3D4D5D6D7
23、 L E OE 1 23456789 11 1213141516171819 Q0Q1Q2Q3Q4Q5Q6Q7 39 39AVR-3805 / AVC-3890 LMS202IMX LMS202IMX Terminal Function Pin NumberPin NamePin Function 1, 3C1+, C1External capacitor connection pins. Recommended external capacitor C1 = 0.1F (6.3V) 2V+Positive supply for TIA/EIA-232E drivers. Recommende
24、d external capacitor C4 = 0.1F (6.3V) 4, 5C2+, C2External capacitor connection pins. Recommended external capacitor C2 = 0.1F (16V) 6VNegative supply for TIA/EIA-232E drivers. Recommended external capacitor C3 = 0.1F (16V) 7, 14T1out, T2outTransmitter output pins conform to TIA/EIA-232E levels. The
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