Denon-AVR2807-avr-sm维修电路原理图.pdf
《Denon-AVR2807-avr-sm维修电路原理图.pdf》由会员分享,可在线阅读,更多相关《Denon-AVR2807-avr-sm维修电路原理图.pdf(130页珍藏版)》请在收音机爱好者资料库上搜索。
1、SERVICE MANUAL MODELAVR-2807 AVR-987 AV SURROUND RECEIVER For U.S.A.,Canada,China HIGH: Bypass mode (through)(2) DGND13Digital GND DOUT12OAudio data digital output FMT017IAudio data format select input 0. See Data Format section.(2) FMT118IAudio data format select input 1. See Data Format section.(2
2、) LRCK10I/OAudio data latch enable input/output(1) MODE019IMode select input 0. See Data Format section.(2) MODE120IMode select input 1. See Data Format section.(2) OSR16IOversampling ratio select input. LOW: 64 fS, HIGH: 128 fS (2) PDWN7IPower-down control, active-low(2) SCKI15ISystem clock input:
3、256 fS, 384 fS, 512 fSor 768 fS (3) TEST9ITest, must be connected to DGND(2) VCC5Analog power supply, 5-V VDD14Digital power supply, 3.3-V VINL1IAnalog input, L-channel VINR2IAnalog input, R-channel VREF13Reference-voltage-1 decoupling capacitor VREF24Reference-voltage-2 decoupling capacitor (1)Schm
4、itt-trigger input (2)Schmitt-trigger input with internal pulldown (50 k typically), 5-V tolerant (3)Schmitt-trigger input, 5-V tolerant 32 AVR-2807 / AVR-987 LC89057W-VF4A (DI : IC101) LC89057W Terminal Function Function Pin No. Pin Name 1RXOUTOInput bi-phase select data output terminal 2RX0ITTL com
5、patible digital data input terminal 3RX1ICoaxial compatible amp built-in digital data input terminal 4RX2ITTL compatible digital data input terminal 5RX3ITTL compatible digital data input terminal 6DGNDDigital GND 7DVDDDigital power 8RX4ITTL compatible digital data input terminal 9RX5/VIITTL compati
6、ble digital data/Validity flag input terminal for modulation 10RX6/UIITTL compatible digital data/User data input terminal for modulation 11DVDDDigital power for PLL 12DGNDDigital GND for PLL 13LPFOPLL loop filter connecting terminal 14AVDDAnalog power for PLL 15AGNDAnalog GND for PLL 16RMCKORMCK cl
7、ock output terminal (256fs, 512fs, XIN, VCO) 17RBCKO/IRBCK clock in/output terminal (64fs) 18DGNDDigital GND 19DVDDDigital power 20RLRCKO/IRLRCK clock in/output terminal (fs) 21RDATAOSerial audio data output terminal 22SBCKOSBCK clock output terminal (32fs, 64fs, 128fs) 23SLRCKOSLRCK clock output te
8、rminal (fs/2, fs, 2fs) 24SDINISerial audio data input terminal 25DGNDDigital GND 26DVDDDigital power 27XMCKOOsc. amp output terminal I/O 36 RERR1RXOUT 35 INT2RX0 34 CKST3RX1 33 AUDIO/VO4RX2 32 EMPHA/UO5RX3 31 DGND6DGND 30 DVDD7DVDD 29 XIN8RX4 28 XOUT9RX5/VI 27 XMCK10RX6/UI 26 DVDD11DVDD 25 DGND12DGN
9、D 24SDIN37DO 23SLRCK38DI 22SBCK39CE 21RDATA40CL 20RLRCK41XMODE 19DVDD42DGND 18DGND43DVDD 17RBCK44TMCK/PIO0 16RMCK45TBCK/PIO1 15AGND46TLRCK/PIO2 14AVDD47TDATA/PIO3 13LPF48TXO/PIOEN TOP VIEW 1RXOUT 32 EMPHA/UO 33 AUDIO/VO 35 INT 40 CL 39 CE 38 DI 28 XOUT 29 XIN 27 XMCK 34 CKST 41 XMODE Input Selector
10、2RX0 3RX1 4RX2 5RX3 8RX4 9RX5/VI 10RX6/UI 37DO 36RERR 21RDATA 24SDIN 16RMCK 17RBCK 20RLRCK 22SBCK 23SLRCK 13LPF 44TMCK/PIO0 45TBCK/PIO1 46TLRCK/PIO2 47TDATA/PIO3 48TXO/PIOEN Clock Selector C bit, U bit PLL Demodulation & Lock Detect Microcontroller I/F Data Selector I/N Modulation or Parallel Port 3
11、3 AVR-2807 / AVR-987 HIN202EIBNZ-T (FR : IC705) Function Pin No. Pin NameI/O * For latch-up countermeasure, perform each power supply ON/OFF in the same timing. 28XOUTOXtal osc. connecting output terminal 29XINIXtal osc. connection, external clock input terminal (24.576MHz or 12.288MHz) 30DVDDDigita
12、l power 31DGNDDigital GND 32EMPHA/UOI/OEmphasis information/U-data output/Chip address setting terminal 33AUDIO/VOI/ONon-PCM detect/V-flag output/ Chip address setting terminal 34CKSTI/OClock switch transition period output/Demodulation master or slave function switching terminal 35INTI/OInterrupt o
13、utput for com (Interrupt factor selectable)/Modulation or general I/O switching terminal 36RERROPLL lock error, data error flag output 37DOOcom I/F, read out data output terminal (3-state) 38DIIcom I/F, write data input terminal 39CEIcom I/F, chip enable input terminal 40CLIcom I/F, clock input term
14、inal 41XMODEISystem reset input terminal 42DGNDDigital GND 43DVDDDigital power 44TMCK/PIO0I/O256fs system clock input for modulation/General I/O in/output terminal 45TBCK/PIO1I/O64fs bit clock input for modulation/General I/O in/output terminal 46TLRCK/PIO2I/Ofs clock input for modulation/General I/
15、O in/output terminal 47TDATA/PIO3I/OSerial audio data input for modulation/General I/O in/output terminal 48TXO/PIOENO/IModulation data output/ General I/O enable input terminal 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 C1+ V+ C1- C2+ C2- R2IN T2OUT VCC T1OUT R1IN R1OUT T1IN T2IN R2OUT GND V- VCC +5V 2
16、 V+ 16 T1OUT T2OUT T1IN T2IN T1 T2 11 10 14 7 +5V 400k +5V 400k R1OUTR1IN R1 1312 5k R2OUTR2IN R2 89 5k +10V TO -10V VOLTAGE INVERTER 0.1 F 6 V- C2+ C2- + 0.1 F 4 5 +5V TO 10V VOLTAGE INVERTER C1+ C1- + 0.1 F 1 3 + 0.1 F + GND 15 34 AVR-2807 / AVR-987 DSD1608PAHR (DI : IC304) VCOM2 VCC7 VCC6 AGND5 V
17、CC5 AGND4 VCC4 AGND3 VCC3 AGND2 VCC2 VCC1 VCOM1 26 25 24 23 22 21 20 19 18 17 16 15 14 40 41 42 43 44 45 46 47 48 49 50 51 52 DSD3 DSD4 DSD5 DSD6 DSD7 DSD8 PDATA1 PDATA2 PDATA3 PDATA4 PBCK PLRCK VDD1 1 2 3 4 5 6 7 8 9 10 11 12 13 DGND1 MDI MS MC MDO ZERO1 ZERO2 ZERO38 VOUT4 VOUT3 VOUT2 VOUT1 AGND1 D
18、SD2 DSD1 DBCK RST VDD2 DSCK PSCK DGND2 VOUT5 VOUT6 VOUT7 VOUT8 AGND6 39 38 37 36 35 34 33 32 31 30 29 28 27 DSD1608 Output Amp and Low-Pass Filter System Clock Enhanced Multilevel Delta-Sigma Modulator DAC ZeroDetectPowerSupply DAC Output Amp and Low-Pass Filter DAC Output Amp and Low-Pass Filter DA
19、C Output Amp and Low-Pass Filter DAC Output Amp and Low-Pass Filter DAC Output Amp and Low-Pass Filter VOUT3 ZERO2 VOUT4 VOUT5 VOUT6 Output Amp and Low-Pass Filter DAC VOUT2 Output Amp and Low-Pass Filter DAC VOUT1 VOUT8 VOUT7 VDD1, 2 VCC17 DGND1, 2 AGND16 ZERO1 ZERO38 System Clock DSCK PSCK PCM I/F
20、 PDATA3 PDATA4 PDATA2 PDATA1 PLRCK PBCK PCM Filter (x8 DF) DSD Filter DSD I/F DSD7 DSD8 DSD6 DSD5 DSD4 DSD3 DSD2 DSD1 DBCK Function ControlMDI MDO MC MS RST VCOM2 VCOM1 35 AVR-2807 / AVR-987 Terminal Functions TERMINAL I/ODESCRIPTION NAMENO. I/ODESCRIPTION AGND113Analogground AGND217Analogground AGN
21、D319Analogground AGND421Analogground AGND523Analogground AGND627Analogground DBCK37IDSD audio data bit clock input (DSD)(3) DGND11Digitalground DGND232Digitalground DSCK34ISystem clock input (DSD). Input frequency is 256, 384, 512 or 768 fs(3) DSD138IDSD audio data input for VOUT1 (DSD)(3) DSD239IDS
22、D audio data input for VOUT2 (DSD)(3) DSD340IDSD audio data input for VOUT3 (DSD)(3) DSD441IDSD audio data input for VOUT4 (DSD)(3) DSD542IDSD audio data input for VOUT5 (DSD)(3) DSD643IDSD audio data input for VOUT6 (DSD)(3) DSD744IDSD audio data input for VOUT7 (DSD)(3) DSD845IDSD audio data input
23、 for VOUT8 (DSD)(3) MC4IMode control clock input(1) MDI2IMode control data input(1) MDO5OMode control read back data output(4) MS3IChip select for mode control(1) PBCK50IAudio data bit clock input (PCM)(3) PDATA146ISerial audio data input for VOUT1 and VOUT2 (PCM)(3) PDATA247ISerial audio data input
24、 for VOUT3 and VOUT4 (PCM)(3) PDATA348ISerial audio data input for VOUT5 and VOUT6 (PCM)(3) PDATA449ISerial audio data input for VOUT7 and VOUT8 (PCM)(3) PLRCK51IAudio data L/R clock input (PCM)(3) PSCK33ISystem clock input (PCM). Input frequency is 128, 192, 256, 384, 512 or 768 fs(3) RST36ISystem
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- Denon AVR2807 avr sm 维修 电路 原理图