Denon-AVR1909-avr-sm维修电路原理图.pdf
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1、Denon Brand Company, D Edge detection is “Ed”; Detection by both shifting is “E Serial data detection is “S” (Serial data output is also “S”). Res: State at reset. “H”= Outputs High Level at reset “L”= Outputs Low Level at reset “Z”= Becomes High impedance mode at reset STBY: State of port when STAN
2、DBY mode. “O/L” = Output port and “L” “I”= Input port Stop: State of port when Stop mode. “O/L”= Output port and “L” “I”= Input port 42 AVR-1909/789, AVC-1909 M3062LFGPGP (IC1405) M3062LFGPGP Terminal Function PinPin NameSymbolI/OTypeDet Op (Int.) Op (Ext.) ResFunction 1P94/TB4VPLD DATAOC-ZVIDEO PLD
3、 control pin 2P93/TB3DIR CEOC-ZDIR control pin(LC89057W-VF4A) 3P92/SOUT3DIR DINOC-ZDIR control pin(LC89057W-VF4A) 4P91/SIN3DIR DOUTI-Lv-EuZDIR control pin(LC89057W-VF4A) 5P90/CLK3DIR CLKOC-ZDIR control pin(LC89057W-VF4A) 6BYTEBYTE-GND(Ext. data bus bit width switching, 16bit:L) 7CNVCSCNVSS-Single-ch
4、ip/Micro-processor mode switching(Normal single-chip:L, Rewrite boot program start:H input set) 8P87VERSTOC-EuZReset for VIDEO ENCODER(ADV7172) 9P86VDRSTOC-EuZReset for VIDEO DECODER(ADV7401) 10RESETSUBRESETI-Lv-EuLReset input 11XOUTX1O-Oscillator connection 12VSSVSS-GND 13XINX2I-Oscillator connecti
5、on 14VCCVCC-+3.3V 15P85/NMINMII-Not used(Fixed to H) 16P84/INT2CEC_INI- E Edge detection is “Ed”; Detection by both shifting is “E Serial data detection is “S” (Serial data output is also “S”). Res: State at reset. “H”= Outputs High Level at reset “L”= Outputs Low Level at reset “Z”= Becomes High im
6、pedance mode at reset STBY: State of port when STANDBY mode. “O/L” = Output port and “L” “I”= Input port Stop: State of port when Stop mode. “O/L”= Output port and “L” “I”= Input port 45 AVR-1909/789, AVC-1909 FLI2310 (IC1011) FLI2310 Block Diagram 1 5 5 1 5 0 1 4 5 1 4 0 1 3 5 1 3 0 1 2 5 1 2 0 1 1
7、 5 1 1 0 1 0 5 1 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 5 6 0 1 0 0 9 5 9 0 8 5 8 0 7 5 7 0 2 0 5 1 9 5 2 0 0 1 6 0 1 6 5 1 7 0 1 7 5 1 8 0 1 8 5 1 9 0 HSYNC1_PORT1 VDD1 B/Cb/D1_0 VSS IN_CLK1_PORT1 FIELD ID1_PORT1 VSYNC1_PORT1 HSYNC2_PORT1 IN_CLK2_PORT1 FIELD ID2_PORT1 VSYNC2_PORT1 B/Cb/D1_6 B/
8、Cb/D1_5 B/Cb/D1_4 B/Cb/D1_3 B/Cb/D1_2 B/Cb/D1_1 B/Cb/D1_7 VDDcore1 VSScore R/Cr/Cb Cr_0 R/Cr/Cb Cr_6 R/Cr/Cb Cr_5 R/Cr/Cb Cr_4 R/Cr/Cb Cr_3 R/Cr/Cb Cr_2 R/Cr/Cb Cr_1 R/Cr/Cb Cr_7 VDD2 VSS G/Y/Y_0 G/Y/Y_1 G/Y/Y_6 G/Y/Y_5 G/Y/Y_4 G/Y/Y_3 G/Y/Y_2 G/Y/Y_7 VDDcore2 VSScore IN_SEL TEST DEV_ADDR1 DEV_ADDR0
9、 SCLK SDATA RESET_N VDD3 VSS SDRAM DATA(0) SDRAM DATA(2) SDRAM DATA(1) SDRAM DATA(3) SDRAM DATA(10) SDRAM DATA(9) SDRAM DATA(8) SDRAM DATA(7) SDRAM DATA(6) SDRAM DATA(5) SDRAM DATA(4) SDRAM DATA(17) SDRAM DATA(16) SDRAM DATA(15) SDRAM DATA(14) SDRAM DATA(12) SDRAM DATA(13) SDRAM DATA(11) VDD4 VSS VD
10、Dcore3 VSScore SDRAM DATA(20) SDRAM DATA(19) SDRAM DATA(18) SDRAM DATA(31) SDRAM DATA(30) SDRAM DATA(29) SDRAM DATA(28) SDRAM DATA(26) SDRAM DATA(27) SDRAM DATA(25) SDRAM DATA(24) SDRAM DATA(23) SDRAM DATA(21) SDRAM DATA(22) VDDcore4 VSScore VSS VDD5 TEST IN SDRAM ADDR(10) SDRAM ADDR(5) SDRAM ADDR(4
11、) SDRAM ADDR(3) SDRAM ADDR(6) SDRAM ADDR(7) SDRAM ADDR(8) SDRAM ADDR(9) VDDcore5 VSScore SDRAM ADDR(0) SDRAM ADDR(1) SDRAM ADDR(2) SDRAM WEN B/U/Pb_OUT_7 VDDcore7 VSScore R/V/Pr_OUT_7 VDD8 VSS G/Y/Y_OUT_7 G/Y/Y_OUT_1 G/Y/Y_OUT_2 G/Y/Y_OUT_3 G/Y/Y_OUT_4 G/Y/Y_OUT_5 G/Y/Y_OUT_6 G/Y/Y_OUT_0 R/V/Pr_OUT_
12、0 R/V/Pr_OUT_1 R/V/Pr_OUT_2 R/V/Pr_OUT_3 R/V/Pr_OUT_4 R/V/Pr_OUT_5 R/V/Pr_OUT_6 B/U/Pb_OUT_0 B/U/Pb_OUT_1 B/U/Pb_OUT_2 B/U/Pb_OUT_3 B/U/Pb_OUT_4 B/U/Pb_OUT_5 B/U/Pb_OUT_6 VSS VDD7 CLKOUT VSScore VDDcore6 TEST OUT1 CTLOUT4 CTLOUT0 CTLOUT1 CTLOUT2 CTLOUT3 TEST OUT0 TEST3 SDRAM CLKIN SDRAM CLKOUT VSS V
13、DD6 SDRAM DQM SDRAM CASN SDRAM BA1 SDRAM BA0 SDRAM CSN SDRAM RASN OE PLL_PVDD PLL_PVSS AVSS_PLL_BE1 AVDD_PLL_BE1 AVSS_PLL_SDI AVSS_PLL_FE AVSS_PLL_BE2 AVDD_PLL_FE AVDD_PLL_SDI AVDD_PLL_BE2 R_VSS R_VDD1.8 R_VSS Reserved Reserved Reserved R_VDD R_VDD R_VDD R_VSS R_VSS R_VSS Reserved Reserved Reserved
14、R_VSS R_VDD R_VSS R_VSS R_VDD R_VDD TEST0 TEST1 TEST2 XTAL IN XTAL OUT VDD9 VSS HSYNC_PORT2 IN_CLK_PORT2 FIELD ID_PORT2 VSYNC_PORT2 VSScore VDDcore8 D1_IN_0 D1_IN_7 D1_IN_6 D1_IN_5 D1_IN_4 D1_IN_3 D1_IN_2 D1_IN_1 Input Processor with Auto Sync and auto Adjust Noise Reducer, Deinterlacer, Frame Rate
15、Converter and SDRAM interface Port 2 8-bit 656 Input Port 1 8/16/24-bit RGB/YCrCb Input Clock Generation PLLs 2Mx32 SDRAM (external) Vertical and Horizontal Scalers Vertical and Horizontal Enhancers Output Processor 16/20/24-bit RBG/YCrCb Digital Outputs 46 AVR-1909/789, AVC-1909 FLI2310 Terminal Fu
16、nction ab e 33 0 pde a s Pin No Pin Name I/O Type Voltage ToleranceDrive Pull up/ PulldownDescription 1HSYNC1_PORT1 Input 5v Horizontal sync or reference -CTL1 of Port 1 2VSYNC1_PORT1 Input 5v Vertical sync or reference -CTL1 of Port 1 3FIELD ID1_PORT1 Input 5v Odd/Even Field identification -CTL1 of
17、 Port 1 4IN_CLK1_PORT1 Input 5v Data Clock input -CTL1 of Port 1 5HSYNC2_PORT1 Input 5v Horizontal sync or reference CTL2 of Port 1 6VSYNC2_PORT1 Input 5v Vertical sync or reference CTL2 of Port 1 7FIELD ID2_PORT1 Input 5v Odd/Even Field identification CTL2 of Port 1 8VDD1 Power 3.3 V - Power pin fo
18、r IO 9VSSGround Ground 10IN_CLK2_PORT1 Input 5v Data Clock input CTL2 of Port 1 11B/Cb/D1_0 Input 5v Port 1 Digital video input (Blue/Cb/D1) 12B/Cb/D1_1 Input 5v Port 1 Digital video input (Blue/Cb/D1) 13B/Cb/D1_2 Input 5v Port 1 Digital video input (Blue/Cb/D1) 14B/Cb/D1_3 Input 5v Port 1 Digital v
19、ideo input (Blue/Cb/D1) 15B/Cb/D1_4 Input 5v Port 1 Digital video input (Blue/Cb/D1) 16VDDcore1 Power 1.8 V - Power pin for core 17VSScore Ground Ground 18B/Cb/D1_5 Input 5v Port 1 Digital video input (Blue/Cb/D1) 19B/Cb/D1_6 Input 5v Port 1 Digital video input (Blue/Cb/D1) 20B/Cb/D1_7 Input 5v Port
20、 1 Digital video input (Blue/Cb/D1) 21R/Cr/Cb Cr_0 Input 5v Port 1 Digital video input (Red/Cr/CrCb) 22R/Cr/Cb Cr_1 Input 5v Port 1 Digital video input (Red/Cr/CrCb) 23R/Cr/Cb Cr_2 Input 5v Port 1 Digital video input (Red/Cr/CrCb) 24R/Cr/Cb Cr_3 Input 5v Port 1 Digital video input (Red/Cr/CrCb) 25R/
21、Cr/Cb Cr_4 Input 5v Port 1 Digital video input (Red/Cr/CrCb) 26R/Cr/Cb Cr_5 Input 5v Port 1 Digital video input (Red/Cr/CrCb) 27R/Cr/Cb Cr_6 Input 5v Port 1 Digital video input (Red/Cr/CrCb) 28R/Cr/Cb Cr_7 Input 5v Port 1 Digital video input (Red/Cr/CrCb) 29G/Y/Y_0 Input 5v Port 1 Digital video inpu
22、t (Green/Y) 30VDD2 Power 3.3 V - Power pin for IO 31VSSGround Ground 32G/Y/Y_1 Input 5v Port 1 Digital video input (Green/Y) 33G/Y/Y_2 Input 5v Port 1 Digital video input (Green/Y) 34G/Y/Y_3 Input 5v Port 1 Digital video input (Green/Y) 35G/Y/Y_4 Input 5v Port 1 Digital video input (Green/Y) 36VDDco
23、re2 Power 1.8 V - Power pin for core 37VSScore Ground Ground 38G/Y/Y_5 Input 5v Port 1 Digital video input (Green/Y) 39G/Y/Y_6 Input 5v Port 1 Digital video input (Green/Y) 40G/Y/Y_7 Input 5v Port 1 Digital video input (Green/Y) 41IN_SEL Output 5v 8 mA Output to select external video mux 42 TEST Inp
24、ut 5v Connect to Ground 43DEV_ADDR1 Input 5v Device address setting 1 44DEV_ADDR0 Input 5v Device address setting 0 47 AVR-1909/789, AVC-1909 Pin No Pin Name I/O Type Voltage ToleranceDrive Pull up/ PulldownDescription 45 SCLK I/O5v 8 mA 2-wire serial control bus clock 46 SDATA I/O5v 8 mA 2-wire ser
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