Denon-AVCA1D-avr-sm维修电路原理图.pdf
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1、Hi-Fi Component AV SURROUND AMPLIFIER / RECEIVER SERVICE MANUAL MODEL AVC-A1D SAFETY PRECAUTIONS.2 SPECIFICATIONS .2 WIRE ARRANGEMENT .3 DISASSEMBLY . 47 LEVEL DIAGRAMS .8,9 CLOCK FLOW Edge detection is “Ed”; Detection by both shifting is “E Serial data detection is “S” (Serial data output is also “
2、S”). Res: State at reset. “H”= Outputs High Level at reset “L”= Outputs Low Level at reset “Z”= Becomes High impedance mode at reset Ini: Initial output state. Function: Function and logical level explanation of signals to be interface. 16 AVC-A1D/AVR-5700 TMP93CS41F (DS: IC301) NameFunction TMP93CS
3、41F Terminal Function Pin No. 1V REFLA/D ref. GND 2A VssA/D GND 3A VccAD +5V 4_NMIINot used (fixed to H) 5P70/TI0_DEMOD RESETOCEdLLDemodulator reset output (L: Reset) 6P71/TO1DEMOD ONOCEdLLDemodulator osc. control output (H: Osc.) 7P72/TO2FAN1OCEdLLFAN control output (H: ON, L: OFF) 8P73/TO3FAN2OCEd
4、LLFAN control output (H: Hi, L: Low Schmitt Trigger input. NOTE2: Pins 22, 24, 25, 26, 27, 28; Schmitt Trigger input with pull-up resister. NOTE3: Pin 23; Schmitt trigger input with pull-down resister. PCM1716E (EX: IC307) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 LR
5、CIN DIN BCKIN CLKO XTI XTO DGND VDD VCC2R AGND2R EXTR NC VOUTR AGND1 M/L IIS M/L IIS MD/DM0 MUTE MODE CS/IWO RST ZERO Vcc2L AGND2L EXTL NC VOUTL Vcc1 Symbol VDD Vss Power terminal +5V Power terminal GND VFLPower terminal FL drive DI CL CE Serial data transfer terminal DI: Data CL: Clock CE: Chip ena
6、ble OSCI OSCO External CR connecting terminal RESSystem reset terminal AM1AM35 AA1AA3 Anode output terminal AA4/G16 AA5/G15 AA6/G14 AA7/G13 AA8/G12 Anode/Grid output terminal G1G11Grid output terminal TESTLSI test terminal Function 25 AVC-A1D/AVR-5700 BR62256F-70LL (DS: IC516) 1 28 14 1 2 3 4 5 6 7
7、8 14 13 12 11 10 9 16 15 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 A/02 VSS Address Buffer Low Decode 262144 bit (512x512) Memory Cell Array Output data control Column Switch Column Decode Address Buffer Cont
8、rol Buffer Input data control A0 A1 A2 A3 A4 A5 A6 A14 I/O 0 I/O 7 CS OE WE A7A12A13 BR62256F-70LL Terminal Function Pin No.SymbolI/OFunction 110A0A9I32K byte memory address input. 1113,I/00I/02I/O8 bit data input/output. 14VssGND 1519I/03I/07I/O8 bit data input/output. 20CSIChip select control inpu
9、t. 21A10I32K byte memory address input. 22OEIOutput enable control input. 2326A11A14I32K byte memory address input. 27WEIWrite enable control input. 28Vcc+5V power supply. BR62256F-70LL Terminal Function 26 AVC-A1D/AVR-5700 AK5351 (DS: IC527) 1 2 3 4 5 6 7 8 16 15 14 13 9 10 11 12 24 23 22 21 20 19
10、18 17 AINR+ AINR- VREF VA AGND AINL+ AINL- TST1 HPFE TST2 TST3 VD VB SMODE1 CMODE SDATA FSYNC LRCK SCLK MCLK PD SMODE2 TST4 DGND VREF AINL+ AINL- AINR+ AINR- AGND VA VD DGND VB CMODE MCLK SMODE2 SMODE1 SCLK LRCK FSYNC SDATA PD HPFE TST1 TST2 TST3 TST4 Modulator Modulator Clock Driver Digital Decimat
11、ion Filter Serial Output Interface Voltage Reference AK5351 Terminal Function Pin No. SymbolI/OFunction 1AINR+IRch analog non-inverted input pin. 2AINRIRch analog inverted input pin 3VREFOVref. output pin (VA-2.6V) 4VAAnalog part power supply pin (+5V) 5AGNDAnalog ground pin 6AINL+ILch analog non-in
12、verted input pin 7AINLILch analog inverted input pin 8TST1Test pin 9HPFEIHi-pass filter enable pin, H: ON, L: OFF 10TST2Test pin 11TEST3Test pin 12VDDigital part power supply pin (+5V) 13DGNDDigital ground pin 14TST4Test pin 15SMODE2IInterface clock select pin 16PDIPower down pin, L: power down mode
13、 17MCLKIMaster clock input pin, CMODE=H: 384fs, L: 256fs 18SCLKI/O Serial data clock pin 19LRCKI/O Input channel select pin 20FSYNCI/O Frame sync clock pin 21SDATAOSerial data output pin 22CMODEIMaster clock select pin, H: MCLK=384fs, L: 256fs 23SMODE2IInterface clock select pin 24VBBulk power suppl
14、y pin (+5V) NJM2229S (VI: IC312) 1 16 Sync Sepa Sync Det Phase Det Vsync Sepa 32fH VCO 1/32 ? ? ? ? ? ? ? ? 27 AVC-A1D/AVR-5700 31 5150 1 30 80 81 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58
15、 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 GND VDD RESET OSCON DATA MCK ML TB IDST IDCK IDO TM0 ECCK DEY DRY MSYC TM1 A0 A1 A2 A3 A4 A5 TM2 TM3 XOUT XIN XNET GND VDD A6 VDD MUTI C1F0 C1F1 C2F0 C2F1 TI
16、8 DASEL DAIN DAOUT DASYO VLDY TI5 MUTO PDDIS TI4 PD0 TD0 TRP TCK TLDB TI3 TI2 VOUT VIN TI1 GND VDD D0 GND A7 VDD A12 A14 WEB A13 A8 A9 GND A11 OEB A10 D7 D6 D5 D4 D3 D2 D1 AVDD AGND BUNR1 TMS ADST1 ADST0 SYST1 SYST0 WINGT GND C9M DOUTB DOUT DIN VDD TM4 AGND CMIN CPIN AVDD Demodulator SYNC Detection
17、& Protection S / P Address Generator A (014) DB (07) OEB WEB C2F1 C2F0 C1F1 C1F0 MUT0 DAOUT CPIN CMIN DOUT DOUTB P0DIS PDO VI VO RESET OSCONC9MMUTIDAINDASEL 46.08MHz Oscillator Timing Generator Error Correction 1/2048 dividing sync 1/2 DAI Controller Phase Comparator GND 9KHz 9.216MHz SW PM4007A (DS
18、: IC512) 28 AVC-A1D/AVR-5700 TC9274N-011 (AU: IC110) 42 1 21 1 2345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 242526272829303132333435363738394041 42VDD VSS S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 GND CK DATA STB S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S1
19、8 18 bit Latch Circuit (Rch) (Lch) Same as Rch Level Shift + Shift Register Circuit MC74HC4053N (VI: IC309) 16 1 8 1 2 V H C X B L L H H X A L H L H X Y0 Y0 Y1 Y1 3 4 5 6 7 89 10 11 16 15 14 13 12 Y1 Y0 Z1 Z Z0 Enable EE GND Vcc Y X1 X X0 C A B Control Inputs Enable Select ON Switches L L L L L L L
20、L L L L L H H H H L L H H L H L H Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1 Y0 Y0 Y1 Y1 X0 X1 X0 X1 X0 X1 X0 X1 None X = Dont Care TC4051BP (VI: 304, 305, 403, 404, 407, 408) 16 1 8 1 2 VEE VDD 2 0 1 3 C A B 3 4 5 6 7 89 10 11 16 15 14 13 12 8 4 6 COM 7 5 INH Vss A B C INH VDD VssVEE 0 1 2 3 4 5 6 7 COMMON OUT C IN O
21、UT C IN OUT C IN OUT C IN OUT C IN OUT C IN OUT C IN OUT C IN LOGIC LEVEL CONVERTER HD14066BP (VI: IC307, 411) 1 7 14 14 13 12 11 10 9 8 INC IN C OUT IN C OUT IN C OUT CONTROL 2 OUT 1 OUT 2 IN 2 CONTROL 3 VSS 1 2 3 4 5 6 7 VDD CONTROL 1 CONTROL 4 IN 4 OUT 4 OUT 3 IN 3 IN 1 OUT 29 AVC-A1D/AVR-5700 1
22、2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 DATA BCLK NC -VDD DGND +VDD WCLK NC 20BIT INVERT -VCC REF DC NC SERVO DC AGND AGND IOUT NC BPO DC +VCC 1 24 12 1234 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 303132 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND DQ3 DQ4 DQ5 DQ6 A1
23、4 A13 A8 A9 OE DQ7 A12 A15 A16 NC VDD WE NC 3 2 4 5 6 7 8 9 10 11 12 24 22 23 21 20 19 18 17 16 15 14 13 1 NC L-OUT L-IN L-LD1 L-LD2 L-A-GND NC CS1 NC GND CK VSSVDD NC R-OUT R-LD1 R-LD2 R-A-GND NC CS2 NC STB DATA R-IN 50k/ 91STEP VR DATA BCLK NC VDD DGND +VDD WCLK NC 20BIT INVERT +VCC BPO DC NC IOUT
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