Denon-AVR550SD-avr-sm维修电路原理图.pdf

《Denon-AVR550SD-avr-sm维修电路原理图.pdf》由会员分享，可在线阅读，更多相关《Denon-AVR550SD-avr-sm维修电路原理图.pdf（71页珍藏版）》请在收音机爱好者资料库上搜索。

1、SERVICE MANUAL AV SURROUND RECEIVER MODELAVR-550SD TOKYO , JAPAN S-1147V.01 DE/CDM 0407 Some illustrations using in this service manual are slightly different from the actual set. Please use this service manual with referring to the operating instructions without fail. For purposes of improvement, s

2、pecifications and design are subject to change without notice. 本文中使用、説明都合上現物 多少異場合。 修理際、必取扱説明書参照上、作業行 。 前、 必読。本機、火災、感電、 対安全性確保、配慮 、法的電気用品安全法 、所定許可得製造。 従際、安全性維 持、記載 注意事項必守。 本機仕様性能改良、予告変更 。 補修用性能部品保有期間、製造打切後8年。 注意 For Japan & Europe model Ver. 1 RadioFans.CN 收音机爱 好者资料库 2 AVR-550SD SAFETY PRECAUTIONS T

3、he following check should be performed for the continued protection of the customer and service technician. LEAKAGE CURRENT CHECK Before returning the unit to the customer, make sure you make either (1) a leakage current check or (2) a line to chassis resistance check. If the leakage current exceeds

4、 0.5 milliamps, or if the resistance from chassis to either side of the power cord is less than 460 kohms, the unit is defective. (1) (2) 500V 1M (1) (2) RadioFans.CN 收音机爱 好者资料库 3 AVR-550SD LEVEL DIAGRAM 4 AVR-550SD 5 AVR-550SD BLOCK DIAGRAM 6 AVR-550SD SEMICONDUCTORS Only major semiconductors are s

5、hown, general semiconductors etc. are omitted to list. 主半導体記載。汎用半導体記載省略。 1. ICs Note: Abbreviation ahead of IC No. indicates the name of P.W.B., etc. 注 ):IC No. 前記号、基板名称表。 MAIN: AUDIO DIGITAL P.W.B. FRONT: FRONT P.W.B. SMPS: SMPS P.W.B. VIDEO: VIDEO P.W.B. I/O: INPUT/OUT PUT P.W.B. ICE1QS01 (SMPS:IC

6、1) Pin Assignmen Block Diagram 1 2 3 45 6 7 8N.C. PCS RZI SRC VCC OUT GND OFC RZI UVLO Q Q SET CLR S R Reference Voltageand Current GND OUT Power Driver Ringing Suppression Time 1V 25mV OFC PCS SRC VCC 1V 2V Burst-Mode + - + - + - + - + - + - + - 3.5V 4.4V + - 4.8V + - 20V Overvoltage Protection Sta

7、rt Digital Processing 50s Timer 50ms Timer ZC-Counter UP/DO-Counter Latch Primary Regulation + - 5V Q Q SET CLR D L 1V + - Foldback Point Corr. 1.5V + - 5.7V 5V 5V 20k 7 AVR-550SD ICE2B265 (SMPS:IC2) ICE2B0565 (SMPS:IC3) Pin Assignmen Block Diagram 1 6 7 8 4 3 2 5 VCCFB Isense Drain SoftS N.C GND Dr

8、ain Thermal Shutdown Tj140C Internal Bias Voltage Reference Leading Edge Blanking 200ns Undervoltage Lockout Oscillator Duty Cycle max Current-Limit Comparator x3.65 Soft-Start Comparator Current Limiting PWM OP Improved Current Mode Soft Start 13.5V 8.5V 6.5V C2 C1 16.5V 4.0V RFB 6.5V Protection Un

9、it Power-Down Reset Power-Up Reset Power Management CSoft-Start 21.5-100kHz CoolSET-F2 Spike Blanking 5 s PWM Comparator R SQ Q Error-Latch C4 5.3V C3 4.8V RSoft-Start Gate Driver G3 G2 G1 G4 T1 Vcsth Propagation-Delay Compensation R S Q Q PWM-Latch 0.72 Clock UFB fosc 100kHz 21.5kHz Standby Unit FB

10、 RSense 0.8V C5 0.3V 10k D1 5.6V CoolMOS Isense GND SoftS VCCDrain 6.5V 5.3V 4.8V 4.0V 8 AVR-550SD TAS5076 (MAIN: IC100) Pin Assignment Block Diagram 22 23 VREGB_CAP DVDD_RCL DVSS_RCL DVDD_PWM DVSS_PWM PWM_AP_4 PWM_AM_4 VALID_4 PWM_BM_4 PWM_BP_4 PWM_AP_5 PWM_AM_5 VALID_5 PWM_BM_5 PWM_BP_5 PWM_AP_6 P

11、WM_AM_6 VALID_6 PWM_BM_6 PWM_BP_6 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NC NC MCLK_IN AVDD_PLL PLL_FLT_OUT PLL_FLT_RET AVSS_PLL NC VREGA_CAP DVSS1 NC RESET ERR_RCVRY MUTE PDN SDA SCL CS0 NC NC 25 26 27 28 79 78 77 76 7580747

12、2 71 7073 29 30 31 32 33 69 68 21 67 66 65 64 34 35 36 37 38 39 40 63 62 61 NC No internal connection AVDD_OSC XTL_IN XTL_OUT AVSS_OSC DVSS PWM_AP1 PWM_AM_1 VALID_1 PWM_BM_1 PWM_BP_1 PWM_AP_2 PWM_AM_2 VALID_2 PWM_BM_2 PWM_BP_2 PWM_AP_3 PWM_AM_3 VALID_3 PWM_BM_3 PWM_BP_3 NC NC NC DBSPD CLIP SDIN1 SDI

13、N2 SDIN3 MCLK_OUT SCLK LRCLK DVDD DVSS VREGC_CAP DEM_SEL2 DEM_SEL1 M_S DVSS1 DVSS1 NC PWM Ch. Output Control AVDD_PLL AVSS_PLL VREGA_CAP VREGB_CAP VREGC_CAP DVDD_RCL DVSS_RCL DVDD_PWM DVSS_PWM Power Supply PLL_FLT_OUT PLL_FLT_RET SCLK LRCLK MCLKOUT SDIN1 SDIN2 SDIN3 MCLK_IN XTAL_OUT XTAL_IN DBSPD SD

14、A SCL CSO PWM_AP_1 PWM_BP_1 PWM_AM_1 Clock, PLL and Serial Data I/F PDN RESET MUTE CLIP ERR_RCVY Serial Control I/F Reset, Pwr Dwn and Status Auto Mute De-emphasis Soft Volume Error Recovery Soft Mute Clip Detect Signal Processing PWM Section PWM Ch. PWM Ch. PWM Ch. PWM Ch. PWM Ch. M_S DM_SEL1 DM_SE

15、L2 VALID_1 PWM_BM_1 PWM_AP_2 PWM_BP_2 PWM_AM_2 VALID_2 PWM_BM_2 PWM_AP_3 PWM_BP_3 PWM_AM_3 VALID_3 PWM_BM_3 PWM_AP_4 PWM_BP_4 PWM_AM_4 VALID_4 PWM_BM_4 PWM_AP_5 PWM_BP_5 PWM_AM_5 VALID_5 PWM_BM_5 PWM_AP_6 PWM_BP_6 PWM_AM_6 VALID_6 PWM_BM_6 9 AVR-550SD TAS5182 (MAIN: IC102,103,104) Pin assignments Bl

16、ock Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 NC NC DVDD DVSS NC DTC_HS DTC_LS OC_HIGH VRFILT AP AM RESET_AB BM BP CP CM RESET_CD DM DP SHUTDOWN ERR0 ERR1 LOW/HIZ DVSS NC NC O

17、C_LOW TEMP GVSS GVDD GLS_A SLS_A SHS_A GHS_A BST_A DHS_A GLS_B SLS_B SHS_B GHS_B BST_B DHS_B GLS_C SLS_C SHS_C GHS_C BST_C DHS_C GLS_D SLS_D SHS_D GHS_D BST_D DHS_D GVDD GVSS DP DM BST_D DHS_D GHS_D SHS_D GLS_D SLS_D CP CM BST_C DHS_C GHS_C SHS_C GLS_C SLS_C BP BM BST_B DHS_B GHS_B SHS_B GLS_B SLS_B

18、 PWM Receiver Timing and Control HS Gate Drive LS Gate Drive AP AM BST_A DHS_A GHS_A SHS_A GLS_A SLS_A Protection Circuitry Status Bandgap Reference VRFILT DTC_HS DTC_LS OC_HIGH TEMP LOW/HIZ A Half-Bridge Driver PWM Receiver Timing and Control HS Gate Drive LS Gate Drive PWM Receiver Timing and Cont

19、rol HS Gate Drive LS Gate Drive PWM Receiver Timing and Control HS Gate Drive LS Gate Drive B Half-Bridge Driver C Half-Bridge Driver D Half-Bridge Driver RESET_AB RESET_CD SHUTDOWN ERR0 ERR1 DVDD DVSS GVDD GVSS GVDD GVDD GVDD GVDD GVDD GVDD GVDD OC_LOW 10 AVR-550SD AK4588 (MAIN: IC219) Pin assignme

20、nts Block Diagram (Top View) CCLK/SCL CDTI/SDA CSN DAUX1 SDTI4 SDTI3 SDTI2 SDTI1 XTL1 XTL0 PDN MASTER DZF2 DZF1 LOUT4 NC ROUT4 NC LOUT3 NC 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67

21、 66 65 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 INT1 BOUT TVDD DVDD DVSS XTO XTI TEST3 MCKO2 MCKO1 COUT UOUT VOUT SDTO2 BICK2 LRCK2 SDTO1 BICK1 LRCK1 CDTO TEST1 RX1 NC RX0 AVSS AVDD VREFH VCOM RIN LIN NC ROUT1 NC LOUT1 NC ROUT2 NC LOUT2 NC ROUT3 INT0 TX1 TX0 MCLK VIN DAUX2 I2C

22、RX7 CAD1 RX6 CAD0 RX5 TEST2 RX4 PVDD R PVSS RX3 NC RX2 Input Selector Clock RecoveryClock Generator DAIF Decoder AC-3/MPEG Detect DEM ?P I/F Audio I/F Xtal Oscillator PDN INT0 LRCK2 BICK2 SDTO2 DAUX2 MCKO2 XTOXTI RPVDDPVSS CDTI CDTO CCLK CSN DVDD DVSS TVDD MCKO1 I2C RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 D

23、IT TX0 Error & Detect STATUS INT1 Q-subcode buffer TX1 B,C,U, VOUT 8 to 3 VIN Audio I/F LPF LPF LPF LPF LPF LPF LOUT1 ROUT1 LOUT2 ROUT2 LOUT3 ROUT3 DAC DATT DEM ADC HPF ADC HPF RIN LIN LRCK1 BICK1 SDTI1 SDTI2 SDTI3 DAUX1 MCLK LRCK BICK SDOUT SDIN1 SDIN2 SDIN3 MCLK SDTO1 Format Converter SDTI4 SDIN4

24、LPF LPF LOUT4 ROUT4 DAC DATT DEM DAC DATT DEM DAC DATT DEM DAC DATT DEM DAC DATT DEM DAC DATT DEM DAC DATT DEM AVDD AVSS 11 AVR-550SD Functions 12 AVR-550SD No. Pin Name I/O Function 55 AVDD - Analog Power Supply Pin, 4.5V?5.5V 56 AVSS - Analog Ground Pin, 0V 57 RX0 I Receiver Channel 0 Pin (Interna

25、l biased pin) This channel is default in serial mode. 58 NC - No Connect This pin should be connected to PVSS. 59 RX1 I Receiver Channel 1 Pin (Internal biased pin) 60 TEST1 I Test 1 Pin This pin should be connected to PVSS. 61 RX2 I Receiver Channel 2 Pin (Internal biased pin) 62 NC - No Connect Th

26、is pin should be connected to PVSS. 63 RX3 I Receiver Channel 3 Pin (Internal biased pin) 64 PVSS - PLL Ground pin 65 R - External Resistor Pin 12k? +/-1% resistor should be connected to PVSS externally. 66 PVDD - PLL Power supply pin, 5.0V 67 RX4 I Receiver Channel 4 Pin (Internal biased pin) 68 TE

27、ST2 I Test 2 Pin This pin should be connected to PVSS. 69 RX5 I Receiver Channel 5 Pin (Internal biased pin) 70 CAD0 I Chip Address 0 Pin (ADC/DAC part) 71 RX6 I Receiver Channel 6 Pin (Internal biased pin) 72 CAD1 I Chip Address 1 Pin (ADC/DAC part) 73 RX7 I Receiver Channel 7 Pin (Internal biased

28、pin) 74 I2C I Control Mode Select Pin. “L”: 4-wire Serial, “H”: I2C Bus 75 DAUX2 I Auxiliary Audio Data Input Pin (DIR/DIT part) 76 VIN I V-bit Input Pin for Transmitter Output 77 MCLK I Master Clock Input Pin 78 TX0 O Transmit Channel (Through Data) Output 0 Pin 79 TX1 O Transmit Channel Output1 pi

29、n When TX bit = “0”, Transmit Channel (Through Data) Output 1 Pin. When TX bit = “1”, Transmit Channel (DAUX2 Data) Output Pin (Default). 80 INT0 O Interrupt 0 Pin 13 AVR-550SD PCM1804 (MAIN: IC212,213,214) Pin Assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VRE

30、FL AGNDL VCOML VINL+ VINL FMT0 FMT1 S/M OSR0 OSR1 OSR2 BYPAS DGND VDD VREFR AGNDR VCOMR VINR+ VINR AGND VCC OVFL OVFR RST SCKI LRCK/DSDBCK BCK/DSDL DATA/DSDR HPF HPF Power Supply CLK Control Delta-Sigma Modulator (L) VREFL VREFR Delta-Sigma Modulator (R) Decimation Filter (L) Decimation Filter (R) S

31、erial Output Interface SCKI VINL+ VINL VCOML AGNDL VREFL VREFR AGNDR VCOMR VINR+ VINR VCCAGNDDGNDVDD OSR0 OSR1 OSR2 S/M FMT0 FMT1 LRCK/DSDBCK BCK/DSDL DATA/DSDR OVFL OVFR BYPAS RST Block Diagram 14 AVR-550SD IS42S16100 (MAIN: IC223) Pin Assignment Block Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

32、 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VCC I/O0 I/O1 GNDQ I/O2 I/O3 VCCQ I/O4 I/O5 GNDQ I/O6 I/O7 VCCQ LDQM WE CAS RAS CS A11 A10 A0 A1 A2 A3 VCC GND I/O15 I/O14 GNDQ I/O13 I/O12 VCCQ I/O11 I/O10 GNDQ I/O9 I/O8 VCCQ NC UDQM CLK CKE NC A

33、9 A8 A7 A6 A5 A4 GND CLK CKE CS RAS CAS WE A11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A10 COMMAND DECODER & CLOCK GENERATOR MODE REGISTER REFRESH CONTROLLER REFRESH COUNTER SELF REFRESH CONTROLLER ROW ADDRESS LATCH MULTIPLEXER ROW ADDRESS BUFFER ROW ADDRESS BUFFER COLUMN ADDRESS LATCH BURST COUNTER COLUMN AD

34、DRESS BUFFER ROW DECODERROW DECODER MEMORY CELL ARRAY BANK 0 COLUMN DECODER MEMORY CELL ARRAY BANK 1 DATA IN BUFFER DATA OUT BUFFER SENSE AMP I/O GATE SENSE AMP I/O GATE 2048 2048 DQM I/O 0-15 Vcc/VccQ GND/GNDQ 11 11 11 11 8 11 11 8 16 1616 16 256 256 15 AVR-550SD NJU7313A (I/O: IC851) BU2090F (FRON

35、T: IC902,607)TS10P05G (SMPS:BD1) 1N4007 ( : IC )SMAB36 ( : IC ) BU2090F (IC302, 1003, 1005) 1 2 3 4 5 6 7 8 18 17 16 15 14 13 12 11Q3 VDD OE Q7 Q8 Q11 Q10 Q9 Q6 VSS DATA CLOCK LCK Q0 Q1 Q2 910Q4Q5 CONTROL CIRCUIT 12-bit SHIFT REGISTER 12-bit STRAGE REGISTER O U TP U T B U F FE R (O P E N D R A IN )

36、21 1:ANODE 2:CATHODE 16 AVR-550SD M66005FP (FRONT: IC901) 14 15 16 CGROM (35bit x 160) CGRAM (35bit x 16) code write data dot data write code select timing clock 59 33 31 24 64 63 62 61 DIG12/ SEG36 DIG13/ SEG37 DIG14/ SEG38 DIG15/ SEG39 SEG00 SEG26 . . . SEG27 SEG34 . . . . . . . . . 12 1 DIG00 DIG

37、11 . . . . . . scan pulse CS SCK SDATA 21 20 XIN XOUT 13 RESET BLOCK DIAGRAM . . . . . . . . . 18 17 2 P0 P1 19 60 22 32 Vcc1 Vcc2 Vss Vp Serial receive circuit Code/ command control circuit Bank 1 : 8bit x 16 Bank 2 : 8bit x 64 Display code RAM Segment output circuit Segment/ Digit select/ output c

38、ircuit Digit output circuit Clock generator Display controller 23 SEG35 . . . . . . . . 17 AVR-550SD SN74VHCU04N (I/O: IC7)RC1117-25 (MAIN: IC215) RC1117-33 (MAIN: IC404) NJM2068M (MAIN: IC220222,231242)MM74LCX244 (MAIN: IC225,227,228) MM74HCT244 (MAIN: IC226) NJM4560M (MAIN: IC230) M29W800AT (MAIN:

39、 IC224) ? ? ? ? ? ? ? ? ? ? 20 1 19 2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 10 1G 2G1A0 2A0 2A3 2Y01Y0 1Y3 1A1 2Y1 1A2 2Y2 1Y1 2A1 1Y2 2A21A3 2Y3 GND VCC 74LCX244 (IC809811) 1 2 3 4 5 6 7 8 20 19 18 16 15 14 13 I3 VCC OE2 O2 I5 O0 I4 O1 I6 OE I0 O4 I1 O5 I2 O6 912 O7O3 1011 GNDI7 TOP VIEW 17 PIN DES

40、CRIPTION Pin Name Address Inputs Symbol A0-A18 Data Input/Outputs, Command InputsDQ0-DQ7 Data Input/OutputsDQ8-DQ14 Data Input/Output or Address InputDQ15A-1 Chip Enable Output Enable Write Enable Reset/Block Temporary Unprotect Ready/Busy OutputRB Byte/Word OrganizationBYTE Supply VoltageVCC Ground

41、VSS No Connected InternallyNC Dont Use as Internally ConnectedDU E G W RP A1A0 A2E A3VSS A4G A5DQ0 A6DQ8 A7DQ1 A17DQ9 A18DQ2 RBDQ10 NCDQ3 NCDQ11 RPVCC WDQ4 NCDQ12 NCDQ5 A8DQ13 A9DQ6 A10DQ14 A11DQ7 A12DQ15A-1 A13VSS A14BYTE A15A16 24 13 12 1 25 36 37 48 M29W800T M29W800T 19 A0-A18 W DQ0-DQ14 M29W800A

42、T E 15 G RP DQ15A-1 BYTE RB VCC Vss 18 AVR-550SD CXP7400P10 (MAIN: IC401) Block Diagram 19 AVR-550SD KIA7805API (MAIN: IC407)BA7626(VIDEO: IC601,603,607) KIA7812API (MAIN: IC406) MM74HC4053MX (VIDEO: IC611613,705) NJM2274 (VIDEO: IC610)BLOCK DIAGRAM 7 8 16 15 14 13 12 11 10 9 Monitor OUT GND IN5 GND

43、 IN4 CTL E IN3 CTL D IN1 CTL A V OUT1 Vcc IN2 CTL B V OUT2 CTL C 6dB 6dB LOGIC LOGIC Note 1: * mark means that feasible for either H or L. Note 2: Each input terminal is provided with sink chip clamp (BA7625). Each input terminal takes 20kohm at the end (BA7626). CDEV OUT 2 LL*IN 1 HL* LH*IN 3 HHLIN

44、 4 HHHIN 5 CDEV OUT 1 LL* HL*IN 2 LH*IN 3 HHLIN 4 HHHIN 5 ABEMONITOR OUT LL*IN 1 HL*IN 2 LH*IN 3 HHLIN 4 HHHIN 5 T T 1 2 VEE 3 4 5 6 7 89 10 11 16 15 14 13 12 Y1 Y0 Z1 Z Z0 Enable GND Vcc Y X1 X X0 C A B X = Dont Care Truth Table Control Inputs Select Enable C BAONSwitches L L LLZ0 Y0 X0 L L LHZ0 Y0

45、 X1 L L HLZ0 Y1 X0 L L HHZ0 Y1 X1 L H LLZ1 Y0 X0 L H LHZ1 Y0 X1 L H HLZ1 Y1 X0 L H HHZ1 Y1 X1 HX X X None Clamp Disc. Vref. 750 1 8 6 72 4 3 Bias Yin Cin C mute GND Vsag Vout Vcc Power Save 5 20 AVR-550SD LC74781 (VIDEO: IC609) 21 AVR-550SD TOP VIEW E B C B C E R1 R2 B C E R1 R2 FRONT VIEW B CE FRON

46、T VIEW BCE KRA Series DTC Series KRC Series R1 10Kohm 47Kohm R2 10Kohm 47Kohm 10Kohm 47Kohm 4.7Kohm R1R2 TRANSISTORS 10Kohm 2SA708 2SC1008 KSP2222A(Q1,Q2) IRFZ24N (AM:Q561564,Q661664,Q761764) KRC107M KRA102M KRA104M KTC3198 2SA933 KTA1266 KSA916 KSC2383(Q3) KSR1004(Q4,Q5) KRA102S KRC102S KRC107S KTA

47、3875S KTA1504S KRC234S KTC2875 KRA102M/S KRA104M KRC107M/S KRC102S KRC2345S 10Kohm FRONT VIEW S D G D S G S D G FRONT VIEW Input Common Output ANODE(A) REFERENCE (R) CATHODE (K) 1 2 4 3 EMITTER COLLECTORANODE CATHODE FRONT VIEW mon ut G D S SPP20N60S5 KA78R15(U4) KA278R09(U5) KIA79151PIFQD5P10 H11A8

48、17(PC16) G D S 22 AVR-550SD DIODE SF3006PT(D11) SFAF808G(G5) FRONT VIEW 1.Anode2.Cathode3.Anode FRONT VIEW 1 3 1 3 1 2 3 23 AVR-550SD 2. FL DISPLAY 15-ST-43GN PIN CONNECTION GRID ASSINMENT 46 45 90 1 24 AVR-550SD ANODE CONNECTION 25 AVR-550SD PRINTED WIRING BOARDS MAIN P.W.B. UNIT COMPONENT SIDE 26

49、AVR-550SD FOIL SIDE 27 AVR-550SD VIDEO P.W.B. UNIT COMPONENT SIDE 28 AVR-550SD FOIL SIDE 29 AVR-550SD FRONT P.W.B. UNIT COMPONENT SIDE 30 AVR-550SD FRONT P.W.B. UNIT FRONT P.W.B. UNIT FRONT P.W.B. UNIT FOIL SIDE FOIL SIDE 31 AVR-550SD SMPS P.W.B. UNIT 32 AVR-550SD NOTE FOR PARTS LIST 5%1/4W 1/16W ss ss ss ss ss ss RD :2B : 1/8 WF :1%P: RC :2E : 1/4 WG :2%NL : RS:2H : 1/2 WJ :5%NB : RW :3A : 1WK :10%FR : RN :3D : 2WM :20%F: