C.Audio-Pulse4x1100-pwr-sm维修电路原理图.pdf

《C.Audio-Pulse4x1100-pwr-sm维修电路原理图.pdf》由会员分享，可在线阅读，更多相关《C.Audio-Pulse4x1100-pwr-sm维修电路原理图.pdf（35页珍藏版）》请在收音机爱好者资料库上搜索。

1、T E C H N I C A L S P E C I F I C A T I O N S Technical Specifications Power RatingsPulse 4x300Pulse 2x650Pulse 2x1100 Measured per channel, both channels driven at 1kHz to no more than 0.1% THD+N 8 Ohms170Wrms400Wrms700Wrms 4 Ohms300Wrms650Wrms1100Wrms 2 Ohms330Wrms*850Wrms*1500Wrms* * Note: 2 Ohm

2、spec is at 1% THD Bridged Mono 16 Ohms400Wrms800Wrms1200Wrms 8 Ohms600Wrms1300Wrms2200Wrms 4 Ohms660Wrms*1700Wrms*3000Wrms* * Note: 4 Ohm bridged spec is at 1% THD Input Sensitivity+1dBu for full output Input Impedance20kOhm Distortion0.006% THD, 1kHz, 1dB below clip, 22kHz measurement bandwidth Fre

3、quency Resp.20Hz to 20kHz, +0/-0.2dB; 120kHz +0/-3dB ControlsPower switch, bridge mode switching, indented level controls (these may be made tamper-proof) IndicatorsMains present, Operate, Signal, Bridge, Clip, Overtemperature, Protect, Remote ProtectionMicroprocessor supervised: overtemperature, DC

4、 on outputs, output stage overload, inrush current surge, mains fail and brownout. Noise50 V/microsecond Damping Factor200 ref 8 Ohm Output Connectors4x300 - Binding post or Speakon 2x650, 2x1100 - Binding post and Speakon Power115 or 230 volts AC nominal, internally selectable, 2000VA, all channels

5、 driven (4x300, 2x650); 3000VA (2x1100) Dimensions3.5 (89mm) x 18.2 (460mm) x 19 (483mm) - with rear rack ears depth 19.5”, -21”, 20” (494, 511, 530mm) Weight24lbs (11kg) Trade Descriptions Act: C Audio have a policy of continued product improvement and accordingly reserve the right to change featur

6、es and specifications without prior notice. Benefits of the Pulse Series Very light weight Switched mode power supplies give solid performance at all power levels Microprocessor protection system Massive heatsinks for cooler operation and higher reliability Binding Post or Speakon output connector o

7、ptions Optional Remote control via C Audio CONNECT Internal crossover card options Pulse 4x300 Into 8 Ohms170W Into 4 Ohms300W Into 2 Ohms330W Pulse 2x650 Into 8 Ohms400W Into 4 Ohms650W Into 2 Ohms850W Pulse 2x1100 Into 8 Ohms700W Into 4 Ohms1100W Into 2 Ohms1500W Power Ratings The Pulse Series com

8、- bines state-of-the-art switched mode power supplies to not only reduce amplifier weight by as much as 70% compared to conventional amps, but also to provide solid, consistent performance at all power levels. Occupying just 2U of rack space, Pulse uses massive heatsinks and front-venting fans to ke

9、ep the electronics really cool, plus a built-in microprocessor which continually monitors all the protection aspects of Pulse - these factors all dramatically enhance reliability. Pulse amplifiers will perform for longer periods than conventional amplifiers at high output levels. The combination of

10、the switched mode PSU and a rugged steel chassis means inherent strength. Cooler, Lighter, Stronger Pulse Series March 2000 RadioFans.CN 收音机爱 好者资料库 Pulse P2X1100 circuit description 1. switching power supply 2. power amplifiers 3. protection 4. frontpanel 2. An error signal caused by incomplete comm

11、on-mode rejection. The error signal is merely attenuated output voltage. As the desired signal, output current, has been full wave rectified and the undesired signal, output voltage, has not, the undesired signal can be removed without corrupting the desired signal by passing it through an integrato

12、r. The raw output current signals from each channel are summed, averaged and inverted by R174, 52, 53, C43 and IC4-A (sheet 4) so that the output at pin1 of IC4-A is a negative DC voltage proportional to the total average output current. This voltage is compared with a threshold, set by R50 and R51

13、to about -2.7V, at IC4-B. R55 provides hysyteresis. If it is higher than the threshold, pin7 will swing to - 13.5V. If it is lower than the threshold then pin7 will swing to +13.5V. IC4-B pin7 drives transistors TR66, 64, 65 and 63. The collectors of these transistors connect to the collectors of TR

14、67, 86, 74& 62. When pin7 swings to +13.5V, TR66, 64, 65& 63 are switched on, the current flow set to 2.5mA by R198 and R197. This forces rail switching off. IC4-B pin7 is connected to the PIC pin22 through R49. Bridge imbalance protection. During normal operation, the bridged output is fully differ

15、ential mode with little or no common- mode signal component. Activation of the output stage current limiters erratically upsets this state, producing a large common-mode error - imbalance - which can destroy the output stages. The bridge imbalance detection is performed by R10,12,13, TR3 and R11. In

16、 two channel mode, the BRIDGE 1+2 line is pulled up to about +13V. this switches TR3 on through R11. The collector of TR3 is connected to pin 23 of IC1 (PIC). The input of the PIC is internally protected by diodes against inputs above +5V and below 0V. so, in two channel mode, pin23 of IC1 receives

17、no signal. In bridge mode, the BRIDGE 1+2 line is held at 0V which switches TR3 off. Now pin 23 of IC1 can receive a signal. R10, 12 sum the output of each channel, the result appearing across R13 which sets the sensitivity. If the bridge is balanced, the voltage across R13 will be zero. If the brid

18、ge is unbalanced then there will be voltage across R13 which is also connected to pin23 of IC1. When an imbalance is detected the PIC immediately mutes both channels for 4 seconds. Then the channels are re-activated. DC Protection Each channels output is connected through R16,R15 to R21 and C16. C16

19、 ensures that only DC is detected. For no DC fault, R32 pulls pin9 of IC1 towards +5V. For a positive DC faults, D4 becomes forward biased and turns TR8 on, pulling pin9 of IC1 (PIC) towards 0V. For a negative DC fault, D3 becomes forward biased which switches TR10 and TR9 on, pulling pin9 of IC1 (P

20、IC) towards 0V. In the event of a DC fault, the PIC switches the PSU off, waits and then tries again. C30,31,35,36 prevent the full-wave recification of PSU noise causing false alarms. 4. Frontpanel and small signal circuits Refer to channel 1 Audio signal enters the amplifier on CN1, CN5, CN8 or CN

21、10 in balanced form, positive phase - hot - on pin 2 of CN8 and negative phase - cold - on pin 3. The signals on each leg will always be out of phase but will not necessarily equal in amplitude. This signal passes through RF1 and RF2 which shunt RF rubbish to chassis. R1 and R4 prevent thumps due to

22、 connection / re-connection. TX1 is an optional audio coupling transformer which is normally not fitted and bypassed by LK2 and LK3. The signal then passes through dc blocking capacitors C3 and C9, through links fitted in the option connectors CN11 and CN12 and on to the frontpanel board via pins 1&

23、2 of CN17. The balanced signal is converted to single-ended by IC1-A (pins1,2,3) and R1,2,3,4,52,59 which form a standard differential amplifier. C25 and C26 shunt HF energy to ground. The signal exits pin1 of IC1-A and is routed to two places, one being the signal led circuit (described later) the

24、other being the level control P1, R5 and analogue switch IC2-A. P1 is a standard linear 10k pot rather than a log taper pot. The level control is given an audio taper (a compromise between log taper and linear taper) by R5 so that the level is attenuated by 10dB at the centre position (rather than 6

25、dB for linear or 20dB for log). The analogue switch is normally closed (pin1 of IC2 low - 0V) allowing operation of the level control. In remote controlled operation (with the remote option installed) the level control is disabled by pulling pin1 of IC2 high (+15V) thus opening the switch. Up to thi

26、s point channel1 and channel2 have identical function. What happens next is determined by the bridge switch (rear panel). 1.bridge mode off the bridge1+2 signal line will be held high by R49 and LD9. Although LD9 will not be illuminated, enough current flows to pull pins 8 & 9 of IC2 high. This open

27、s the switches IC2-C (pins 10 &11) and IC2-D (pins 6 & 7). Channel 1 signal enters pin 5 of IC1 which is configured to have a gain of +14.5dB by R17, R15 and continues through R7 to pin13 of CN1. Channel 2 signal enters pin 5 of IC3 which is configured to have a gain of +14.5dB by R30, R16 and conti

28、nues through R14 to pin15 of CN1. 2.bridge mode on the bridge1+2 signal line will be held low by the rear panel bridge switch. LD9 will be illuminated and pins 8 & 9 of IC2 will be pulled low (0V). This closes the switches IC2-C (pins 10 &11) and IC2-D (pins 6 & 7). Channel 1 signal enters pin 5 of

29、IC1 which is configured as a to have a gain of +14.5dB by R17, R15 and continues through R7 to pin13 of CN1. Closure of switch IC2-C connects this signal to pin6 of IC3 through R29 which, in conjunction with R30, configures IC3-B to be a unity gain inverter (R16 does not affect the signal gain). Thu

30、s, the channel1 signal is inverted and passed to channel 2 through R14 to pin15 of CN1. Channel 2 signal is shorted to ground through switch IC2-D. Signal LED The signal is coupled from pin1 if IC1 through C10 and across R35 to IC8 pin3. Initial conditions: C15 has 0V across it and LD1 is off. Pins

31、1,2 and 3 of IC8 are at 0V. A signal appears at pin3 of IC8. It is moving from 0V in a positive direction. Due to the large open-loop gain of IC8, pin1 will move in a positive direction at a much greater rate. This will forward bias the diode in D1 (which connects pin1 to the top of C15) and charge

32、up C15. When enough volts have accumulated on C15, LD1 will conduct, its current limited by R34 and R33. R34 and R33 also form a potential divider applying negative feedback to pin2 thus setting the sensitivity of the circuit. The signal at pin3 of IC7 now moves in a negative direction. Therefore pi

33、n1 will move negative at a much greater rate and the diode in D1 (which connects pin1 to the top of C15) becomes reverse biased. The other diode in D1 ( connecting pin1 to pin2) now conducts preventing saturation of the op-amp. LD1 will continue to glow by discharging C15 until the voltage on C15 fa

34、lls below that required to turn LD1 on. Clip LED The clip detector circuit is on the main board consisting of IC5-B, R87,148,101,153,158 & R173 and C89&93. These are connected to form a differential amplifier which samples the voltage between the base of TR30 and the base of TR31. This voltage is th

35、e difference between the input and the divided down output of the amplifier. When the amplifier clips, there is a large difference between the input and the divided down output which is amplified by the differential amplifier. This passes from pin1, through R173 to pin 23 of CN17 and onto the frontp

36、anel board. Here it is full-wave rectified by D5 and D6, smoothed by C17 and the resultant voltage illuminates LD5 through R45. 5. System management Power for the management system is provided by a conventional transformer-rectifier- capacitor-regulator supply. TX3 receives mains through F1 and is n

37、ot affected by the main chassis fuse (F2). The secondary passes through fuse F3 to bridge rectifier BR1. The rectified AC is then smoothed by C11 producing about 25Vdc for 230Vac mains or 12.5Vdc for 115Vac mains. The regulator circuit used is similar to the internal workings of an LM317. TR1 and TR

38、2 form a darlington pass transistor. R9 provides bias current for D1, a TL431. D1 combines a voltage reference of 2.5V and an amplifier in one package. C6 prevents oscillations. R5 and R6 set the output voltage to 5V - 2.5V x (1+R5/R6). The brain behind the operations is IC1, a MICROCHIP PIC16C57 mi

39、croprocessor. This is not a re-programmable part. The clock is set to 3.58MHz by XT1, C19, C17 and pins27, 28 of IC1. Each of the heatsinks has an LM35DZ, IC11 and IC12, attached close to the front of the unit. The voltage at pin2 of each of these gives a measurement of the temperature - 10mV per 0C

40、 starting at 0V for 00C. Continuing with channel1, the temperature signal is filtered by R263 and C26 and enters pin3 of IC2-A. this is configured to give a gain of x10.2 giving 102mV per 0C. The output at pin1 of IC2-A is coupled through R42 to pin24 of CN11. It is also coupled through potential di

41、vider R38, R39 to pin 6 of IC2-B at which point the signal is 34mV per 0C. IC2-B (pins 5, 6, 7), R45, C34, R27 and IC1 pins 6, 7 comprise an analogue to digital converter. At the start of conversion, pin6 of IC1 is set to 0V for 1ms and discharges C34 through R27. Pin 6 of IC1 is then set to high im

42、pedance mode. At this point, pin7 of IC2-B is at -13.5V because pin5 is at a lower voltage than pin6. Now, the voltage on C34 ramps at about 600mV/ms because it is being charged by R45. The ramp stops at about 5.5V, limited by the protection diode on pin6 of IC1. The voltage on C34 is connected to p

43、in5 of IC2-B so that when the ramp voltage exceeds the temperature voltage on pin6, pin7 changes to +13.5V. pin7 is connected to pin7 of IC1 through R31. In this way, the IC1 has a measure of time between the start of conversion and when pin7 (IC1) receives a logic high which is proportional to the

44、voltage at pin6 of IC2-B. After 18.32ms the conversion cycle starts again. The heatsink temperature measurements are used to control the fan speed and to mute overheating channels. Take, for instance, channel 1. If the heatsink temperature exceeds 900C then channel 1 is muted. Channel 1 will be re-a

45、ctivated when the heatsink temperature falls below 750C. The two fans are connected in parallel, the negative wires connected to -15V, the positive wires connected through R17 to R18 and the collector of TR6. If the heatsink temperature is less than 550C then pin17 of IC1 (PIC) is set to +5V. This t

46、urns TR5 on which in turn switches TR6 off leaving the fans powered through R18. If the heatsink exceeds 550C then pin17 of IC1 is set to 0V, switching TR5 off and therefore TR6 on so that TR6 shorts R18 out. The fans are returned to slow speed when the heatsink temperature falls below 500C. TR4 and TR7 are used to completely switch the fans off when a brown-out condition is detected.