HarmanKardon-AVR3550-avr-sm维修电路原理图.pdf

AVR 3550 Audio/VideoReceiver Service Manual AVR 3550 Power for the Digital Revolution RadioFans.CN Technical Specifications Audio Section Stereo Mode Continuous Average Power (FTC) 65 Watts per channel, 20Hz20kHz, < 0.07% THD, both channels driven into 8 ohms Five-Channel Surround Modes Power Per Individual Channel Front L Amplifier is in protection mode Check speaker wire connections for shorts at receiver and light around power switch is reddue to possible shortspeaker ends Amplifier is in protection mode Contact your local Harman Kardon service center, which you can due to internal problemslocate by visiting our Web site at No sound from surround or Incorrect surround mode Select a mode other than Stereo or Dolby 3 Stereo center speakers Input is monaural There is no surround information from mono sources Incorrect configuration Check speaker mode configuratioin Stereo or Mono program material The surround decoder may not create center- or rear-channel information from nonencoded programs Unit does not respond to Weak batteries in remote Change remote batteries remote commands Wrong device selected Press the AVR selector Remote sensor is obscured Make certain front-panel sensor is visible to remote or connect remote sensor Intermittent buzzing in tuner Local interference Move unit or antenna away from computers, fluorescent lights, motors or other electrical appliances Letters flash in the channel indicator Digital audio feed paused Resume play for DVD display and digital audio stops Check that Digital Input is selected RadioFans.CN AMPLIFIER SECTION BIAS ADJUSTMENT CUP11517X (MAIN PCB) Measurement condition . No input signal or volume position is minimum. Standard value. . Ideal current = 48mA ( 5%) . Ideal DC Voltage = 21.12mV ( 5%) DC VOLTMETER.Connect to CN61, CN62, CN63, CN64, CN65 NO.ChannelAdjust forAdjustment 1Front Left21.12mV (5%) VR61 CN61 VR61 2Front Right21.12mV (5%) 21.12mV (5%) 21.12mV (5%) 21.12mV (5%) VR62 CN62 VR62 3Center VR63 CN63 VR63 4Surround Left VR64 CN64 VR64 5Surround Right VR65 VR65 CN65 n Block Diagram SCFDACDATT DZFL1 LOUT1+ LOUT1- SCFDACDATT DZFR1 ROUT1+ ROUT1- SCFDACDATT DZFL2 LOUT2+ LOUT2- SCFDACDATT DZFR2 ROUT2+ ROUT2- SCFDACDATT DZFL3 LOUT3+ LOUT3- SCFDACDATT DZFR3 ROUT3+ ROUT3- Audio I/F Control Register AK4356 MCLK LRCK BICK MCKO LRCK BICK XTI XTO Controller CS CCLK CDTI LRCK BICK SDOUT1 SDOUT2 SDOUT3 AC3 SDTI1 SDTI2 SDTI3 LOUT1- ROUT1+ 1 LOUT1+ 44 2 DZFL23 DZFR14 DZFL15 CAD06 CAD17 PDN8 BICK9 MCLK10 DVDD11 ROUT1-43 LOUT2+42 LOUT2-41 ROUT2+40 ROUT2-39 LOUT3+38 LOUT3-37 ROUT3+36 ROUT3-35 AVSS34 DVSS12 SDTI113 SDTI214 SDTI315 LRCK16 SMUTE17 CCLK18 CDTI19 CSN20 DFS021 CKS022 33 32 31 30 29 28 27 26 25 24 23 AVDD VREFH DZFR2 DZFL3 DZFR3 DZFE DIF2 DIF1 DIF0 CKS2 CKS1 AK4356VQ Top View D/A CONVERTER IC PIN ASSIGNMENT & BLOCK DIAGRAM PIN ASSIGNMENT (TOP VIEW) PIN/FUNCTION No.Pin NameI/OFunction 1LOUT1-ODAC1 Lch Negative Analog Output Pin 2LOUT1+ODAC1 Lch Positive Analog Output Pin 3DZFL2ODAC2 Lch Zero Input Detect Pin 4DZFR1ODAC1 Rch Zero Input Detect Pin 5DZFL1ODAC1 Lch Zero Input Detect Pin 6CAD0IChip Address 0 Pin 7CAD1IChip Address 1 Pin 8PDNIPower-Down & Reset Pin When “L”, the AK4356 is powered-down and the control registers are reset to default state. If the state of CAD0-1 changes, then the AK4356 must be reset by PDN. 9BICKIAudio Serial Data Clock Pin 10MCLKIMaster Clock Input Pin 11DVDD-Digital Power Supply Pin, +4.75+5.25V 12DVSS-Digital Ground Pin 13SDTI1IDAC1 Audio Serial Data Input Pin 14SDTI2IDAC2 Audio Serial Data Input Pin 15SDTI3IDAC3 Audio Serial Data Input Pin 16LRCKIAudio Input Channel Clock Pin 17SMUTEISoft Mute Pin (Note) When this pin goes to “H”, soft mute cycle is initialized. When returning to “L”, the output mute releases. 18CCLKIControl Data Clock Pin 19CDTIIControl Data Input Pin 20CSNIChip Select Pin This pin should be held to “H” except for access. D/A CONVERTER IC PIN FUNCTION (AK4356VQ) : IC78 No.Pin NameI/OFunction 21DFS0IDouble Speed Sampling Mode 0 Pin (Note) “L”: Normal Speed, “H”: Double Speed at DFS1 bit = “0”. 22CKS0IInput Clock Select 0 Pin (Note) 23CKS1IInput Clock Select 1 Pin (Note) 24CKS2IInput Clock Select 2 Pin (Note) 25DIF0IAudio Data Interface Format 0 Pin (Note) 26DIF1IAudio Data Interface Format 1 Pin (Note) 27DIF2IAudio Data Interface Format 2 Pin (Note) 28DZFEIZero Input Detect Enable Pin (Note) 29DZFR3ODAC3 Rch Zero Input Detect Pin 30DZFL3ODAC3 Lch Zero Input Detect Pin 31DZFR2ODAC2 Rch Zero Input Detect Pin 32VREFHIPositive Voltage Reference Input Pin, AVDD 33AVDD-Analog Power Supply Pin 34AVSS-Analog Ground Pin, +4.75+5.25V 35ROUT3-ODAC3 Rch Negative Analog Output Pin 36ROUT3+ODAC3 Rch Positive Analog Output Pin 37LOUT3-ODAC3 Lch Negative Analog Output Pin 38LOUT3+ODAC3 Lch Positive Analog Output Pin 39ROUT2-ODAC2 Rch Negative Analog Output Pin 40ROUT2+ODAC2 Rch Positive Analog Output Pin 41LOUT2-ODAC2 Lch Negative Analog Output Pin 42LOUT2+ODAC2 Lch Positive Analog Output Pin 43ROUT1-ODAC1 Rch Negative Analog Output Pin 44ROUT1+ODAC1 Rch Positive Analog Output Pin Note:SMUTE, DFS0, CKS0, CKS1, CKS2, DIF0, DIF1, DIF2, DZFE pins are ORed with serial control register. Input Selector Clock RecoveryClock Generator DAIF Decoder AC-3/MPEG Detect DEM P I/F Audio I/F Xtal Oscillator PDN INT0P/S=”L” LRCK BICK SDTO DAUX MCKO2 XTOXTI RAVDDAVSS CDTI CDTO CCLK CSN DVDD DVSS TVDD MCKO1 IIC RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 DIT TX0 Error & Detect STATUS INT1 Q-subcode buffer TX1 B,C,U,VOUT 8 to 3 VIN Serial Control Mode Input Selector Clock RecoveryClock Generator DAIF Decoder AC-3/MPEG Detect DEM Audio I/F Xtal Oscillator PDN INT0P/S=”H” LRCK BICK SDTO DAUX XTOXTI RAVDDAVSS CM1 CM0 OCKS1 OCKS0 DVDD DVSS TVDD IPS1 RX0 RX1 RX2 RX3 IPS0 DIF0 DIF1 DIF2 DIT TX0 Error & Detect STATUS INT1 TX1 B,C,U,VOUT 4 to 2 VIN MCKO2 MCKO1 Parallel Control Mode BLOCK DIAGRAM IPS0/RX4 RX3 1 AVSS 48 2 DIF0/RX53 TEST24 DIF1/RX65 AVSS6 DIF2/RX77 IPS1/IIC8 P/SN9 XTL010 XTL1 AVSS 47 RX246 45 44 AVSS43 RX042 AVSS41 VCOM40 R 39 AVDD38 TVDD13 NC14 TX015 TX116 BOUT17 18 UOUT19 VOUT20 DVDD21 DVSS22 MCKO123 36 35 34 33 32 31 30 29 28 27 26 INT0 OCKS0/CSN/CAD0 OCKS1/CCLK/SCL CM1/CDTI/SDA CM0/CDTO/CAD1 PDN XTI XTO DAUX MCKO2 BICK AK4114VQ Top View COUT TEST1 RX1 INT137LRCK24 11 VIN1225SDTO DIR IC PIN ASSIGNMENT & BLOCK DIAGRAM PIN ASSIGNMENT (TOP VIEW) PIN/FUNCTION No. Pin Name I/O Function IPS0 I Input Channel Select 0 Pin in Parallel Mode 1 RX4 I Receiver Channel 4 Pin in Serial Mode (Internal biased pin) 2 NC(AVSS) I No Connect No internal bonding. This pin should be connected to AVSS. DIF0 I Audio Data Interface Format 0 Pin in Parallel Mode 3 RX5 I Receiver Channel 5 Pin in Serial Mode (Internal biased pin) 4 TEST2 I TEST 2 pin This pin should be connect to AVSS. DIF1 I Audio Data Interface Format 1 Pin in Parallel Mode 5 RX6 I Receiver Channel 6 Pin in Serial Mode (Internal biased pin) 6 NC(AVSS) I No Connect No internal bonding. This pin should be connected to AVSS. DIF2 I Audio Data Interface Format 2 Pin in Parallel Mode 7 RX7 I Receiver Channel 7 Pin in Serial Mode (Internal biased pin) IPS1 I Input Channel Select 1 Pin in Parallel Mode 8 IIC I IIC Select Pin in Serial Mode. “L”: 4-wire Serial, “H”: IIC 9 P/SN I Parallel/Serial Select Pin “L”: Serial Mode, “H”: Parallel Mode 10 XTL0 I Xtal Frequency Select 0 Pin 11 XTL1 I Xtal Frequency Select 1 Pin 12 VIN I V-bit Input Pin for Transmitter Output 13 TVDD I Input Buffer Power Supply Pin, 3.3V or 5V 14 NC I No Connect No internal bonding. This pin should be open or connected to DVSS. 15 TX0 O Transmit Channel (Through Data) Output 0 Pin 16 TX1 O When TX bit = “0”, Transmit Channel (Through Data) Output 1 Pin. When TX bit = “1”, Transmit Channel (DAUX Data) Output Pin (Default). 17 BOUT O Block-Start Output Pin for Receiver Input “H” during first 40 flames. 18 COUT O C-bit Output Pin for Receiver Input 19 UOUT O U-bit Output Pin for Receiver Input 20 VOUT O V-bit Output Pin for Receiver Input 21 DVDD I Digital Power Supply Pin, 3.3V 22 DVSS I Digital Ground Pin 23 MCKO1 O Master Clock Output 1 Pin 24 LRCK I/O Channel Clock Pin 25 SDTO O Audio Serial Data Output Pin 26 BICK I/O Audio Serial Data Clock Pin 27 MCKO2 O Master Clock Output 2 Pin 28 DAUX I Auxiliary Audio Data Input Pin 29 XTO O Xtal Output Pin 30 XTI I Xtal Input Pin DIR IC PIN FUNCTION (AK4114VQ) : IC75 PIN/FUNCTION (Continued) No.Pin NameI/OFunction 31PDNI Power-Down Mode Pin When “L”, the AK4114 is powered-down and reset. CM0IMaster Clock Operation Mode 0 Pin in Parallel Mode CDTOOControl Data Output Pin in Serial Mode, IIC= “L”.32 CAD1IChip Address 1 Pin in Serial Mode, IIC= “H”. CM1IMaster Clock Operation Mode 1 Pin in Parallel Mode CDTIIControl Data Input Pin in Serial Mode, IIC= “L”.33 SDAI/OControl Data Pin in Serial Mode, IIC= “H”. OCKS1IOutput Clock Select 1 Pin in Parallel Mode CCLKIControl Data Clock Pin in Serial Mode, IIC= “L”34 SCLIControl Data Clock Pin in Serial Mode, IIC= “H” OCKS0IOutput Clock Select 0 Pin in Parallel Mode CSNIChip Select Pin in Serial Mode, IIC=”L”.35 CAD0IChip Address 0 Pin in Serial Mode, IIC= “H”. 36INT0OInterrupt 0 Pin 37INT1OInterrupt 1 Pin 38AVDDIAnalog Power Supply Pin, 3.3V 39R- External Resistor Pin 18k +/-1% resistor should be connected to AVSS externally. 40VCOM- Common Voltage Output Pin 0.47F capacitor should be connected to AVSS externally. 41AVSSIAnalog Ground Pin 42RX0I Receiver Channel 0 Pin (Internal biased pin) This channel is default in serial mode. 43NC(AVSS)I No Connect No internal bonding. This pin should be connected to AVSS. 44RX1IReceiver Channel 1 Pin (Internal biased pin) 45TEST1I TEST 1 pin. This pin should be connected to AVSS. 46RX2IReceiver Channel 2 Pin (Internal biased pin) 47NC(AVSS)I No Connect No internal bonding. This pin should be connected to AVSS. 48RX3IReceiver Channel 3 Pin (Internal biased pin) Note 1. All input pins except internal biased pins should not be left floating. PIN ASSIGNMENT (74HCU04AFN : IC71,72 ) LOGIC SYMBOL TRUTH TABLE 1 2 3 4 5 6 7 1A 1Y 2A 2Y 3A 3Y GND 6A 6Y 5A 5Y 4A 4Y Vcc14 13 12 11 10 9 8 A L H Y H L 1A (1) (3) (5) (9) (11) (13) 2A 3A 4A 5A 6A 1Y 2Y 3Y 4Y 5Y 6Y (2) (4) (6) (8) (10) (12) 2000 Fairchild Semiconductor CorporationDS August 1984 Revised January 2000 MM74HC4066 Quad Analog Switch Quad Analog Switch (74HC4066D) : IC42 General Description The MM74HC4066 devices are digitally controlled analog switches utilizing advanced silicon-gate CMOS technology. These switches have low “ON” resistance and low “OFF” leakages. They are bidirectional switches, thus any analog input may be used as an output and visa-versa. Also the MM74HC4066 switches contain linearization circuitry which lowers the “ON” resistance and increases switch lin- earity. The MM74HC4066 devices allow control of up to 12V (peak) analog signals with digital control signals of the same range. Each switch has its own control input which disables each switch when LOW. All analog inputs and out- puts and digital inputs are protected from electrostatic damage by diodes to VCC and ground. Features I Typical switch enable time: 15 ns I Wide analog input voltage range: 012V I Low “ON” resistance: 30 typ. (MM74HC4066) I Low quiescent current: 80 A maximum (74HC) I Matched switch characteristics I Individual switch controls Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Schematic DiagramConnection Diagram Top View Truth Table Order NumberPackage NumberPackage Description MM74HC4066MM14A14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow MM74HC4066SJM14D14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC4066MTCMTC1414-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC4066NN14A14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide InputSwitch CTLI/OO/I L“OFF” H“ON” Modulator MCLK AINL LRCK SCLK SDTO DIF VCOM Clock Divider AINR AGNDVA Decimation Filter Serial I/O Interface Voltage Reference TTL DGNDVD TST Modulator Decimation Filter PDN A/D CONVERTER IC (AK5380VT) : IC77 1AINR AINL VCOM NC AGND VA VD DGND Top View 2 3 4 5 6 7 8 TST TTL PDN DIF SCLK MCLK LRCK SDTO 16 15 14 13 12 11 10 9 PIN ASSIGNMENT (TOP VIEW) A/D CONVERTER IC PINouts (AK5380VT) : IC77 PIN/FUNCTION No.Pin NameI/ODescription 1AINRIRch Analog Input Pin 2AINLILch Analog Input Pin 3NC-NC Pin No internal bonding. 4VCOMOCommon Voltage Output Pin Normally connected to AGND with a 0.1F ceramic capacitor in parallel with an electrolytic capacitor less than 2.2F. 5AGND-Analog Ground Pin, 0V 6VA-Analog Power Supply Pin, +4.5+5.5V 7VD-Digital Power Supply Pin, +2.7+5.5V(fs=48kHz), +4.5+5.5V(fs=96kHz) 8DGND-Digital Ground Pin, 0V 9SDTOOSerial Data Output Pin Data bits are presented MSB first, in 2s complement format. This pin is “L” in the power-down mode. 10LRCKILeft/Right Channel Select Pin The fs clock is input to this pin. 11MCLKIMaster Clock Input Pin 12 SCLKISerial Data Input Pin Output data is clocked out on the falling edge of SCLK. 13PDNIPower-Down Pin When “L”, the circuit is in power-down mode. The AK5380 should always be reset upon power-up. 14DIFISerial Interface Format Pin “L”: MSB justified, “H”: I2S 15TTLIDigital Input Level Select Pin “L”: CMOS level (VD=2.75.5V), “H”: TTL level (VD=4.55.5V) 16TSTITest Pin (Internal pull-down pin) This pin should be left open. Note: All input pins except pull-down pins should not be left floating. A/D CONVERTER IC PIN FUNCTION (AK5380VT) : IC77 CM2054C Ise Electronics Corporation :Grid Assignment Scale 3:1 Unit : mm Sheet 4/5 G10G9G8G7G6G5G4G3G2G1 G3-G10G2G1 S16 S15 S13 S12 S14 S17 S1 S2 S4 S6S5 S8S9 S11 S10 S3 S7 S7 S6 S2 S1 S3 S5 S4 S16 S15 S11 S10 S12 S14 S13 S18 S21 S3S9 S15 S12S6 S1 S19 S22 S4 S7S13 S16 S10 CM2054C Ise Electronics Corporation :Anode & Grid Assignment G1 Sheet 5/5 NL (F2) F1,F2:Filament G1-G10:GridS1-S24:Anode NP:No Pin NL:No Lead PIN ASSIGNMENT Pin No. AssignmentF2NPNL S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9S8S7S6S5S4S3S2 Pin No. AssignmentNLNLNLNL G10 G9G8G7G6G5G4G3G2G1NLNPF1 NL (F1) S1 G2G3G4G5G6G7G8G9G10 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S1 LFE S3 S4 SL S6 S7 SBL S9 S10 SR S12 S13 SBR S15 S16 R S18 S19 C S21 S22 L NIGHT S1 S2 S3 S4 S5 S6 S7 S10 S11 S12 S13 S14 S15 S16 PRESET SLEEP MULTI S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 dB ST MEM KHz MHz LOGIC 7 C M S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 TUNED VMAx N F S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 TA AUTO DSP S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 RDS OSD S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 ANALOG 3 ST S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12