HarmanKardon-AVR2550-avr-sm维修电路原理图.pdf

AVR 2550 Audio/VideoReceiver Service Manual AVR 2550 Power for the Digital Revolution RadioFans.CN TECHNICAL SPECIFICATIONS Technical Specifications Audio Section Stereo Mode Continuous Average Power (FTC) 50 Watts per channel, 20Hz20kHz, < 0.07% THD, both channels driven into 8 ohms Five-Channel Surround Modes Power Per Individual Channel Front L Amplifier is in protection mode Check speaker wire connections for shorts at receiver and light around power switch is reddue to possible shortspeaker ends Amplifier is in protection mode Contact your local Harman Kardon service center, which you can due to internal problemslocate by visiting our Web site at No sound from surround or Incorrect surround mode Select a mode other than Stereo or Dolby 3 Stereo center speakers Input is monaural There is no surround information from mono sources Incorrect configuration Check speaker mode configuratioin Stereo or Mono program material The surround decoder may not create center- or rear-channel information from nonencoded programs Unit does not respond to Weak batteries in remote Change remote batteries remote commands Wrong device selected Press the AVR selector Remote sensor is obscured Make certain front-panel sensor is visible to remote or connect remote sensor Intermittent buzzing in tuner Local interference Move unit or antenna away from computers, fluorescent lights, motors or other electrical appliances Letters flash in the channel indicator Digital audio feed paused Resume play for DVD display and digital audio stops Check that Digital Input is selected RadioFans.CN AMPLIFIER SECTION BIAS ADJUSTMENT CUP11517X (MAIN PCB) Measurement condition . No input signal or volume position is minimum. Standard value. . Ideal current = 48mA ( 5%) . Ideal DC Voltage = 21.12mV ( 5%) DC VOLTMETER.Connect to CN61, CN62, CN63, CN64, CN65 NO.ChannelAdjust forAdjustment 1Front Left21.12mV (5%) VR61 CN61 VR61 2Front Right21.12mV (5%) 21.12mV (5%) 21.12mV (5%) 21.12mV (5%) VR62 CN62 VR62 3Center VR63 CN63 VR63 4Surround Left VR64 CN64 VR64 5Surround Right VR65 VR65 CN65 TRANSISTOR, REGULATOR IC BLOCK DIAGRAM TO-92M 1. Emitter 2. Collector 3. Base 1. Emitter 2. Collector 3. Base KTC2874B KRA107M 2SA1360O KTD600KG KTD1302T KTC3200GR KTA1271Y KTA1268GR KTC3198Y KSC2785Y KRC107M 2SC3423O 1. Emitter 2. Collector 3. Base TO-126 TO-92 123 123 123 1. Base 2. Collector 3. Emitter KSA614Y TO-220 123 1. INPUT 2. GND 3. OUTPUT MC7815C MC7805C TO-220 123 1. GND 2. INPUT 3. OUTPUT MCNJM7905 MC7915C TO-220 123 1. Base 2. Collector 3. Emitter 2SB1647 2SD2560 KTA1024Y KSC2316Y 1. Emitter 2. Collector 3. Base TO-3P TO-92L 123 1 2 3 1dB VR latch 8dB VR latch 1dB VR latch 8dB VR latch 3 to 7 decoder 4 to 13 decoder 1dB VR latch Shift register (32BIT) Strobe generate circuit Level shift circuit 8dB VR latch 2 3L- OUTA NCVSSVDDTEST L- INA4 5L- A- GNDA L- OUTB6 L- INB7 8L- A- GNDB L- OUTC9 L- INC10 12CS1 GND13 CK14 L- A- GNDC11 3L- OUTA L- INA4 5L- A- GNDA L- OUTB Same as L- ch Circuit 6 L- INB7 8L- A- GNDB L- OUTC9 L- INC10 12CS1 GND13 CK14 L- A- GNDC11 12827 TC9482F (ELECTRONIC VOLUME/INPUT) : IC31TC9482F (ELECTRONIC VOLUME/INPUT) : IC31 GND 1 TC9215AF OFF 2 3S10 S11 S12 S20 S21 S41 S40 S42 S34 S32 S31 S30 Vss DD 4 5 6 7 16 V 15 14 13 12 11 10 89 TC9215AF (TONE CONTROL : IC80) BLOCK DIAGRAM LEVEL SHIFTER 2 1 2 3 4 1 5 6 2 7 8 3 1 2 3 4 1 5 6 2 7 8 3 1 3 4 5 6 7 8 9 10 1428 11 12 13 27 26 25 24 23 22 21 20 19 18 17 16 15 LATCH CIRCUIT SHIFT REGISTER LEVEL SHIFTER LATCH CIRCUIT L-SR-S VssGNDVDD L-S L-S L-S L-COM L-S L-S L-COM L-S L-S L-COM ST R-S R-S R-S R-COM R-S R-S R-COM R-S R-S R-COM DATA CK LEVEL SHIFTER 2 1 2 3 1 4 5 6 2 7 8 3 1 2 3 1 4 5 6 2 7 8 3 1 3 4 5 6 7 8 9 10 1428 11 12 13 27 26 25 24 23 22 21 20 19 18 17 16 15 LATCH CIRCUIT SHIFT REGISTER LEVEL SHIFTER LATCH CIRCUIT L-S R-S VssGNDVDD L-S L-S L-COM L-S L-S L-S L-COM L-S L-S L-COM ST R-S R-S R-COM R-S R-S R-S R-COM R-S R-S R-COM DATA CK TC9164AF (FUNCTION/INPUT) : IC22 BLOCK DIAGRAM TC9163AF (FUNCTION/INPUT) : IC20 BLOCK DIAGRAM LEVEL SHIFTER 2 1 2 1 3 4 2 5 6 3 7 4 1 2 1 3 4 2 5 6 3 7 4 1 3 4 5 6 7 8 9 10 1428 11 12 13 27 26 25 24 23 22 21 20 19 18 17 16 15 LATCH CIRCUIT SHIFT REGISTER LEVEL SHIFTER LATCH CIRCUIT L-SR-S VssGNDVDD L-S L-COM L-S L-S L-COM L-S L-S L-COM L-S L-COM ST R-S R-COM R-S R-S R-COM R-S R-S R-COM R-S R-COM DATA CK LEVEL SHIFTER 2 1 2 1 3 4 2 5 6 3 7 4 1 2 1 3 4 2 5 6 3 7 4 1 3 4 5 6 7 8 9 10 1428 11 12 13 27 26 25 24 23 22 21 20 19 18 17 16 15 LATCH CIRCUIT SHIFT REGISTER LEVEL SHIFTER LATCH CIRCUIT L-SR-S VssGNDVDD L-S L-COM L-S L-S L-COM L-S L-S L-COM L-S L-COM ST R-S R-COM R-S R-S R-COM R-S R-S R-COM R-S R-COM DATA CK TC9162AF (FUNCTION/INPUT : IC30) BLOCK DIAGRAM TC9162AF (FUNCTION/INPUT : IC30) BLOCK DIAGRAM No. 5606-3/13 Top view PIN ASSIGNMENT (TOP VIEW) PinPin No.FunctionI/OHandling when unused VFL1, 13Driver block power supply connection. (Both pins must be connected.) VDD60Logic block power supply connection. Provide a voltage between 4.5 and 5.5 V. VSS57Power supply connection. Connect to the ground. OSCI59 Oscillator connection. An oscillator circuit is formed by connecting an external resistor IGND OSCO58 and capacitor to these pins. OOPEN Display off control input. BLK61 BLK = Low (VSS) . Display off. (S1 to S43 and G1 to G11 at VFLlevel.) IGND BLK = High (VDD) . Display on. Note that serial data can be transferred while the display is turned off. CL63 DI64IGND CE62 G1 to G112 to 12Digit outputs. These pins are P-channel open drain outputs with pull-down resistors.OOPEN S1 to S4356 to 14 Segment outputs for displaying the display data transferred by serial data input. These pins OOPEN are P-channel open drain outputs with pull-down resistors. Serial data transfer inputs. These pins must be connected to the system microcontroller. CL: Synchronization clock DI: Transfer data CE: Chip enable BLOCK DIAGRAM VFD DRIVER IC PIN FUNCTION (LC75725E) : IC74 PIN No.Pin NameI/OFunction 1,12,23+VD1-Digital Power supply. Normally +2.5v 2,13,24DGND-Digital Ground 3AUD3OSPDIF transmitter output/Digital audio output(N.C) 4WRIHost write strobe pin(connected to GND with an external resistor) 5RDIHost parallel output enable pin(pulled up with an external resistor) 6 CS_DA I SPI Serial data input pin 7CS_CKISerial control clock input pin 8EMAD7I/O 9EMAD6I/O 10EMAD5I/O 11EMAD4I/OSerial data IN/OUTPUT pins(pulled up with an external resistor) 14EMAD3I/O 15EMAD2I/O 16EMAD1I/O 17EMAD0I/O 18CS_CEIHost parallel chip select pin 19SCDIO(AK_DOUT)OSerial control port data ouput pin 20INTREQOControl port interrupt request output pin 21EXTMEMI/OExternal Memory Chip Selector(pulled up with an external resistor) 22SDATAN1(SDI)IPCM audio data input number 1 pin 25SCLKN1(BICK)IPCM audio input bit clock pin 26LRCLKN1(LRCK)IPCM audio input sample rate clock pin 27CMPDAT(SDI)IPCM audio data input number 2 pin 28CMPCLK(BICK)IPCM audio input bit clock pin 29CREQ(LRCK)IPCM audio input sample rate clock pin 30CLKIN(XIN)IMaster clock input(used external clock) 31CLKSEL(GND)IDSP clock mode select pin: connect the GND 32FILT1Connects to an external filter for the on-chip phase-locked loop 33FILT1Connects to an external filter for the on-chip phase-locked loop 34+2.5V-Analog Power supply for clock generator . Normally +2.5V 35AGND-Analog ground supply for clock generator PLL. 36RESET(CS_RST)IMaster reset input pin 37DBDATA-Reserved pin and should be pulled up with an external resistor. 38DBCLK-Reserved pin and should be pulled up with an external resistor. 39AUD2(SDO2)OPCM multi-format digital-audio data ouput2 pin 40AUD1(SDO1)OPCM multi-format digital-audio data ouput1 pin 41AUD0(SDO0)OPCM multi-format digital-audio data ouput0 pin 42LRCLKIAudio output sample rate clock pin 43SCLK(BICK)IAudio ouput bit clock pin 44MCLKIAudio master clock output pin AUDIO DSP (CS493263 - CLG : IC79) CMPDAT SDATAN2 CMPCLK SCLKN2 CMPREQ LRCLKN2 SCLKN1 STCCLK2 LRCLKN1 SDATAN1 CLKIN CLKSEL FILTDFILTSVAAGNDDGND(3:1)VD(3:1) XMT95 AUDA LRCLK SCLK MCLK DC DD EXTMEM. GPIO8 A800T INTERQ A1, SCDIN A0, SCCLK CS STC Parallel or Serial Host Interface RESET SCDIO, SCDOUT, PSEL, GPIO9 WR, DR, EMWR, GPIO10 RD, R/W, EMOE, GPIO11 DATA7:0, EMAD7:0, GPIO7:0 Compressed Data Input Interface RAM Program Memory ROM Program Memory RAM Data Memory RAM Output Buffer Output Formatter ROM Data Memory PLL Clock Manager RAM Input Buffer 24-Bit DSP Processing Digital Audio Input Interface Framer Shifter Input Buffer Controller PIN ASSIGNMENT.(CS493263) (TOP VIEW) BlOCK DIAGRAM(CS493263) VD1 DGND1 AUDATA3, XMT958 WR,DS,EMWR,GPIO10 RD,R/W,EMOE,GPIO11 A1,SCDIN A0,SCCLK DATA7,EMAD7,GPIO7 CS493XXX-CLG 44-pin PLCC Top View DATA6,EMAD6,GPIO6 DATA5,EMAD5,GPIO5 DATA4,EMAD4,GPIO4 DATA3,EMAD3,GPIO3 DATA2,EMAD2,GPIO2 DATA1,EMAD1,GPIO1 DATA0,EMAD0,GPIO0 VD2 DGND2 CS SCDIO,SCDOUT,PSEL,GPIO9 ABOOT,INTREQ EXTMEM,GPIO8 SDATAN1 MCLK SCLK LRCLK AUDATA0 AUDATA1 AUDATA2 DC 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 654321 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 DD RESET AGND FILT2 CLKSEL CLKIN CMPREQ,LRCLKN2 VA FILT1 CMPDAT,SCLKN2,RCV958 CMPCLK,SCLKN2 LRCLKN1 VD3 SCLKN1,STCCLK2 DGND3 CM2054C Ise Electronics Corporation :Grid Assignment Scale 3:1 Unit : mm Sheet 4/5 G10G9G8G7G6G5G4G3G2G1 G3-G10G2G1 S16 S15 S13 S12 S14 S17 S1 S2 S4 S6S5 S8S9 S11 S10 S3 S7 S7 S6 S2 S1 S3 S5 S4 S16 S15 S11 S10 S12 S14 S13 S18 S21 S3S9 S15 S12S6 S1 S19 S22 S4 S7S13 S16 S10 CM2054C Ise Electronics Corporation :Anode & Grid Assignment G1 Sheet 5/5 NL (F2) F1,F2:Filament G1-G10:GridS1-S24:Anode NP:No Pin NL:No Lead PIN ASSIGNMENT Pin No. AssignmentF2NPNL S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9S8S7S6S5S4S3S2 Pin No. AssignmentNLNLNLNL G10 G9G8G7G6G5G4G3G2G1NLNPF1 NL (F1) S1 G2G3G4G5G6G7G8G9G10 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S1 LFE S3 S4 SL S6 S7 SBL S9 S10 SR S12 S13 SBR S15 S16 R S18 S19 C S21 S22 L NIGHT S1 S2 S3 S4 S5 S6 S7 S10 S11 S12 S13 S14 S15 S16 PRESET SLEEP MULTI S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 dB ST MEM KHz MHz LOGIC 7 C M S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 TUNED VMAx N F S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 TA AUTO DSP S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 RDS OSD S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 ANALOG 3 ST S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 COAX 1 2 3 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 OPT 1 2 3 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 HDCD MP3 PCM PLD D DTS 12345678910111213141516171819 202122232425262728293031323334353637383940414243444546 Modulator MCLK AINL LRCK SCLK SDTO DIF VCOM Clock Divider AINR AGNDVA Decimation Filter Serial I/O Interface Voltage Reference TTL DGNDVD TST Modulator Decimation Filter PDN A/D CONVERTER IC (AK5380VT) : IC77 1AINR AINL VCOM NC AGND VA VD DGND Top View 2 3 4 5 6 7 8 TST TTL PDN DIF SCLK MCLK LRCK SDTO 16 15 14 13 12 11 10 9 PIN ASSIGNMENT (TOP VIEW) A/D CONVERTER IC (AK5380VT) : IC77 PIN/FUNCTION No.Pin NameI/ODescription 1AINRIRch Analog Input Pin 2AINLILch Analog Input Pin 3NC-NC Pin No internal bonding. 4VCOMOCommon Voltage Output Pin Normally connected to AGND with a 0.1F ceramic capacitor in parallel with an electrolytic capacitor less than 2.2F. 5AGND-Analog Ground Pin, 0V 6VA-Analog Power Supply Pin, +4.5+5.5V 7VD-Digital Power Supply Pin, +2.7+5.5V(fs=48kHz), +4.5+5.5V(fs=96kHz) 8DGND-Digital Ground Pin, 0V 9SDTOOSerial Data Output Pin Data bits are presented MSB first, in 2s complement format. This pin is “L” in the power-down mode. 10LRCKILeft/Right Channel Select Pin The fs clock is input to this pin. 11MCLKIMaster Clock Input Pin 12 SCLKISerial Data Input Pin Output data is clocked out on the falling edge of SCLK. 13PDNIPower-Down Pin When “L”, the circuit is in power-down mode. The AK5380 should always be reset upon power-up. 14DIFISerial Interface Format Pin “L”: MSB justified, “H”: I2S 15TTLIDigital Input Level Select Pin “L”: CMOS level (VD=2.75.5V), “H”: TTL level (VD=4.55.5V) 16TSTITest Pin (Internal pull-down pin) This pin should be left open. Note: All input pins except pull-down pins should not be left floating. A/D CONVERTER IC PIN FUNCTION (AK5380VT) : IC77 SCFDACDATT DZFL1 LOUT1+ LOUT1- SCFDACDATT DZFR1 ROUT1+ ROUT1- SCFDACDATT DZFL2 LOUT2+ LOUT2- SCFDACDATT DZFR2 ROUT2+ ROUT2- SCFDACDATT DZFL3 LOUT3+ LOUT3- SCFDACDATT DZFR3 ROUT3+ ROUT3- Audio I/F Control Register AK4356 MCLK LRCK BICK MCKO LRCK BICK XTI XTO Controller CS CCLK CDTI LRCK BICK SDOUT1 SDOUT2 SDOUT3 AC3 SDTI1 SDTI2 SDTI3 n Block Diagram LOUT1- ROUT1+ 1 LOUT1+ 44 2 DZFL23 DZFR14 DZFL15 CAD06 CAD17 PDN8 BICK9 MCLK10 DVDD11 ROUT1-43 LOUT2+42 LOUT2-41 ROUT2+40 ROUT2-39 LOUT3+38 LOUT3-37 ROUT3+36 ROUT3-35 AVSS34 DVSS12 SDTI113 SDTI214 SDTI315 LRCK16 SMUTE17 CCLK18 CDTI19 CSN20 DFS021 CKS022 33 32 31 30 29 28 27 26 25 24 23 AVDD VREFH DZFR2 DZFL3 DZFR3 DZFE DIF2 DIF1 DIF0 CKS2 CKS1 AK4356VQ Top View D/A CONVERTER IC PIN ASSIGNMENT & BLOCK DIAGRAM PIN ASSIGNMENT (TOP VIEW) PIN/FUNCTION No.Pin NameI/OFunction 1LOUT1-ODAC1 Lch Negative Analog Output Pin 2LOUT1+ODAC1 Lch Positive Analog Output Pin 3DZFL2ODAC2 Lch Zero Input Detect Pin 4DZFR1ODAC1 Rch Zero Input Detect Pin 5DZFL1ODAC1 Lch Zero Input Detect Pin 6CAD0IChip Address 0 Pin 7CAD1IChip Address 1 Pin 8PDNIPower-Down & Reset Pin When “L”, the AK4356 is powered-down and the control registers are reset to default state. If the state of CAD0-1 changes, then the AK4356 must be reset by PDN. 9BICKIAudio Serial Data Clock Pin 10MCLKIMaster Clock Input Pin 11DVDD-Digital Power Supply Pin, +4.75+5.25V 12DVSS-Digital Ground Pin 13SDTI1IDAC1 Audio Serial Data Input Pin 14SDTI2IDAC2 Audio Serial Data Input Pin 15SDTI3IDAC3 Audio Serial Data Input Pin 16LRCKIAudio Input Channel Clock Pin 17SMUTEISoft Mute Pin (Note) When this pin goes to “H”, soft mute cycle is initialized. When returning to “L”, the output mute releases. 18CCLKIControl Data Clock Pin 19CDTIIControl Data Input Pin 20CSNIChip Select Pin This pin should be held to “H” except for access. D/A CONVERTER IC PIN FUNCTION (AK4356VQ) : IC78 No.Pin NameI/OFunction 21DFS0IDouble Speed Sampling Mode 0 Pin (Note) “L”: Normal Speed, “H”: Double Speed at DFS1 bit = “0”. 22CKS0IInput Clock Select 0 Pin (Note) 23CKS1IInput Clock Select 1 Pin (Note) 24CKS2IInput Clock Select 2 Pin (Note) 25DIF0IAudio Data Interface Format 0 Pin (Note) 26DIF1IAudio Data Interface Format 1 Pin (Note) 27DIF2IAudio Data Interface Format 2 Pin (Note) 28DZFEIZero Input Detect Enable Pin (Note) 29DZFR3ODAC3 Rch Zero Input Detect Pin 30DZFL3ODAC3 Lch Zero Input Detect Pin 31DZFR2ODAC2 Rch Zero Input Detect Pin 32VREFHIPositive Voltage Reference Input Pin, AVDD 33AVDD-Analog Power Supply Pin 34AVSS-Analog Ground