HarmanKardon-AVR2650-avr-sm3维修电路原理图.pdf

256M Double Data Rate Synchronous DRAM A3S56D30FTP A3S56D40FTP PIN FUNCTION CLK, /CLKInput Clock: CLK and /CLK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CLK and negative edge of /CLK. Output (read) data is referenced to the crossings of CLK and /CLK (both directions of crossing). CKEInput Clock Enable: CKE controls Power Down and Self Refresh. Taking CKE LOW provides Precharge Power Down or Self Refresh (all banks idle), or Active Power Down (row active in any bank). Taking CKE HIGH provides Power Down exit or Self Refresh exit. After Self Refresh is started, CKE becomes asynchronous input. Power Down and Self Refresh is maintained as long as CKE is LOW. /CSInputChip Select: When /CS is HIGH, any command means No Operation. /RAS, /CAS, /WEInputCombination of /RAS, /CAS, /WE defines basic commands. A0-12Input A0-12 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-12. The Column Address is specified by A0-9(x8) and A0-8(x16). A10 is also used to indicate precharge option. When A10 is HIGH at a Read / Write command, an Auto Precharge is performed. When A10 is HIGH at a Precharge command, all banks are precharged. BA0,1Input DQ0-7 (x8), DQ0-15 (x16), Input / Output DQS (x8) Vdd, VssPower SupplyPower Supply for the memory array and peripheral circuitry. VddQ, VssQPower SupplyVddQ and VssQ are supplied to DQ, DQS buffers. Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with Active, Precharge, Read, Write commands. Data Input/Output: Data bus Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS correspond to the data on DQ8-DQ15 SYMBOLTYPEDESCRIPTION DM (x8)Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7; UDM corresponds to the data on DQ8-DQ15. Input / Output VREFInputSSTL_2 reference voltage. UDQS, LDQS (x16) UDM, LDM (x16) AVR 2650 AVR 2650 harman/kardonharman/kardon RadioFans.CN 12-Bit, 170 MHz Video and Graphics Digitizer with 3D Comb Filter Decoder and Quad HDMI 1.4 Fast Switching Receiver PRELIMINARY ADV7844 FEATURES Quad HDMI 1.4 Fast Switching Receiver 170 MHz Video and Graphics Digitizer 3D Comb Filter Video Decoder SCART Fast Blank Support Adaptive HDMI Equaliser Integrated CEC Controller HDMI Repeater Support Advanced VBI data slicer Video and Graphics Digitizer Four 170 MHz, 12-bit ADCs, 12-channel analog input mux 525i-/625i-component analog input 525p-/625p-component progressive scan support 720p-/1080i-/1080p-component HDTV support Low refresh rates (24/25/30 Hz) support for 720p/1080p Digitizes RGB graphics up to 1600 1200 at 60 Hz (UXGA) 3D Video Decoder NTSC/PAL/SECAM color standards support NTSC/PAL 2D/3D motion detecting comb filter Advanced time-base correction (TBC) with frame synchronization Interlaced-to-progressive conversion for 525i and 625i IF compensation filters Vertical peaking and horizontal peaking filters Robust synchronization extraction for poor video source 4:1 HDMI 1.4 225 MHz Receiver Fast-Switching of HDMI ports 2:2 HEAC muxing support 2 HEAC channel support 2 Ethernet Interfaces for HEC Support SPDIF interface for ARC support. 3D Video format support including frame packing 1080p 24Hz, 720p 50 Hz, 720p 60Hz Full colorimetry support including sYCC601, Adobe RGB, Adobe YCC 601 36-/30-bit Deep Color and 24-bit color support HDCP 1.3 support with internal HDCP Keys +5V Detect and Hot plug assert for each HDMI port Full HDMI Audio Support including HBR, DSD, DST Advanced Audio mute feature Flexible digital audio output interfaces Supports up to 5 SPDIF outputs, Supports up to 4 I2S outputs General Highly flexible 36-bit pixel output interface Internal EDID RAM for HDMI and graphics Dual STDI (standard identification) function support Any-to-any, 3 3 color space conversion (CSC) matrix 2 programmable interrupt request output pins Simultaneous analog processing and HDMI monitoring APPLICATIONS Advanced TVs PDP HDTVs LCD TVs (HDTV ready) LCD/DLP rear projection HDTVs CRT HDTVs LCoS HDTVs AVR video receivers LCD/DLP front projectors HDTV STBs with PVR Projectors FUNCTIONAL BLOCK DIAGRAM 36-BIT YCbCr /RGB ADV7844 SCART RGB + CVBS CVBS YC HDMI 4 HDMI 3 HDMI 2 HDMI 1 HD YPbPr INPUT MUX SD/PS YPbPr SDRAM SCART G SCART B SCART R CVBS CVBS SCART CVBS I2S 36 4 Y/G Pb/B Pr/R 48 GRAPHICS RGB ADC ADC ADC ADC TO AUDIO PROCESSOR TMDS DDC TMDS DDC TMDS DDC TMDS DDC DEEP COLOR HDMI Rx HDCP KEYS SPDIF DSD SDP CLK HS/VS FIELD/DE CLK HS/VS FIELD/DE CLK HS/VS FIELD/DE CVBS 3D YC S-VIDEO SCART CP YPbPr 525p/625p 720p/1080i 1080p/UXGA RGB OUTPUT MUX OUTPUT MUX HBR AUDIO OUTPUT5 MCLK SCLKMCLK SCLK DATA DATA FAST SWITCH SPDIF HEAC ETHERNET 1 ETHERNET 2 Figure 1. AVR 2650 AVR 2650 harman/kardonharman/kardon 122 ADV7844 PRELIMINARY Rev. PrC| Page 4 of 35 DETAILED FUNCTIONAL BLOCK DIAGRAM ANALOG FRONT END CLAMPADC0 LLC GENERATION CONTROL CONTROL AND DATA SYNC PROCESSING AND CLOCK GENERATION FILTER DDCA_SDA / DDCA_SCL YPrPb CVBS YC SCART RGB RGB AOUT CEC AVLINK 12 CLAMPADC1 12 CLAMPADC2 12 CLAMPADC3 12 12-CHANNEL INPUT MATRIX HS/CS,VS/FIELD TRI1 TO TRI4 SYNC1 SYNC2 HS_IN1 VS_IN1 HS_IN2/TRI5 VS_IN2/TRI6 TRI-LEVEL SLICER SCL SDA CONTROL INTERFACEI2C PLL RXA_C RXB_C RXC_C RXD_C RXA_0 RXA_1 RXA_2 RXB_0 RXB_1 RXB_2 RXC_0 RXC_1 RXC_2 RXD_0 RXD_1 RXD_2 AVLINK CONTROLLER CEC CONTROLLER EDID/ REPEATER CONTROLLER EQUALIZERSAMPLER EQUALIZERSAMPLER EQUALIZERSAMPLER EQUALIZERSAMPLER HDCP BLOCK PACKET PROCESSOR DIGITAL PROCESSING BLOCK COMPONENT PROCESSOR VIDEO DATA PROCESSOR VIDEO OUTPUT FORMATTER INT1 LLC P0 TO P11 P12 TO P23 P24 TO P35 INT2 STANDARD DEFINITION PROCESSOR (SDP) HS/CS VS/FIELD DE SYNC_OUT 12 12 12 MUX PACKET/ INFOFRAME MEMORY 4:2:2 TO 4:4:4 CONVERSION AUDIO PROCESSOR 2D COMB3D COMBTBC MACROVISION DETECTION STANDARD AUTODECTION CTI and LTI VERTICAL PEAKING HORIZONTAL PEAKING FASTBLANK OVERLAY CONTROL DDR/SDR-SDRAM INTERFACE INTERLACE TO PROGRESSIVE CONVERSION COLOR SPACE CONVERSION ANCILLARY DATA FORMATTER I2C READBACK FAST I2C INTERFACE VSI DECODER ACTIVE PEAK AND HSYNC DEPTH NOISE AND CALIBRATION OFFSET ADDER GAIN CONTROL DIGITAL FINE CLAMP PROGRAMMABLE DELAY CP CSC AND DECIMATION FILTERS AV CODE INSERTION STANDARD IDENTIFICATION SYNC EXTRACT (ESDP) MACROVISION AND CGMS DETECTION SYNC SOURCE AND POLARITY DETECT AUDIO OUTPUT FORMATTER AP0 MCLK SCLK AP1 AP2 AP3 AP4 AP5 FASTSWITCHING BLOCK + HDMI DECODE + MUX RXB_5V / HPDB RXA_5V / HPDA 5V DETECT AND HPD CONTROLLER RXD_5V / HPDD RXC_5V / HPDC HDCP EEPROM DEEP COLOR CONVERSION DDCB_SDA / DDCB_SCL DDCC_SDA / DDCC_SCL DDCD_SDA / DDCD_SCL (A) (B) (C) (A) (B) (C) (D) INTERRUPT CONTROLLER TTX_SDA / TTX_SCL DECIMATION FILTERS HDMI ETHERNET CHANNEL supports TMDS logic level. 48 TXC+ HDMI output Differential Clock Output. Differential clock output at the TMDS clock rate; supports TMDS logic level. 49 TXGND Ground TXAVDD Ground. 50 TX0 HDMI output Differential Output Channel 0 Complement. Differential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 51 TX0+ HDMI output Differential Output Channel 0 True. Differential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 52 TXGND Ground TXAVDD Ground. 53 TX1 HDMI output Differential Output Channel 1 Complement. Differential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 54 TX1+ HDMI output Differential Output Channel 1 True. Differential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 55 TXAVDD Power 1.8 V Power Supply for TMDS Outputs. 56 TX2 HDMI output Differential Output Channel 2 Complement. Differential output of the red data at 10 the pixel clock rate; supports TMDS logic level. AVR 2650 AVR 2650 harman/kardonharman/kardon 138 ADV3014 ADI Confidential Rev. Sp0 | Page 10 of 16 Pin No. Mnemonic Type Description 57 TX2+ HDMI output Differential Output Channel 2 True. Differential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 58 TXGND Ground TXAVDD Ground. 59 CEC Digital I/O Consumer Electronics Control Channel. This pin is 5 V tolerant. 60 DGND Ground DVDD Ground. 61 DVDD Power Digital Supply Voltage (1.8 V). 62 ALSB Digital input This pin is used to set the I2C address of the Rx IO and the Tx main maps. 63 CS Digital input Chip Select Pin. This pin must be set low or left floating for the chip to process I2C messages that are destined for the ADV3014. The ADV3014 ignores I2C messages that it receives if this pin is high. 64 EP_SCK Digital output SPI Clock Interface for the EDID. 65 EP_CS Digital output SPI Chip Selected Interface for the EDID. 66 EP_MOSI Digital output SPI Master Out/Slave In for the EDID. 67 EP_MISO Digital input SPI Master In/Slave Out for the EDID. 68 TEST1 Test pin Connect to ground. 69 TEST2 Test pin Connect to ground. 70 TEST3 Test pin Connect to ground. 71 TEST4 Test pin Connect to ground. 72 DGNDIO Ground DVDDIO Ground. 73 DVDDIO Power Digital I/O Supply Voltage (3.3 V). 74 TEST5 Test pin Connect to ground. 75 TEST6 Test pin Connect to ground. 76 TEST7 Test pin Connect to ground. 77 TEST8 Test pin Connect to ground. 78 SDATA Digital I/O I2C Port Serial Data Input/Output Pin. SDATA is the data line for the control port. 79 SCL Digital input I2C Port Serial Clock Input. SCL is the clock line for the control port. 80 DGND Ground DVDD Ground. 81 DVDD Power Digital Supply Voltage (1.8 V). 82 INT1 Digital output Interrupt Pin. This pin can be active low or active high. When status bits change, this pin is triggered. The events that trigger an interrupt are under user control. 83 INT2 Digital output Interrupt Pin. This pin can be active low or active high. When status bits change, this pin is triggered. The events that trigger an interrupt are under user control. 84 INT_TX Digital output Interrupt; Open Drain. A 2 k pull-up resistor to the microcontroller I/O supply is recommended. 85 DGNDIO Ground DVDDIO Ground. 86 DVDDIO Power Digital I/O Supply Voltage (3.3 V). 87 TEST9 Test pin Leave floating. 88 TEST10 Test pin Leave floating. 89 TEST11 Test pin Leave floating. 90 TEST12 Test pin Leave floating. 91 TEST13 Test pin Leave floating. 92 DGND Ground DVDD Ground. 93 DVDD Power Digital Supply Voltage (1.8 V). 94 TEST14 Test pin Leave floating. 95 TEST15 Test pin Leave floating. 96 TEST16 Test pin Leave floating. 97 RESET Digital input System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset the ADV3014 circuitry. 98 PWRDN Digital input Active-Low Power-Down Pin. If used, this pin should be pulled high to power up the ADV3014. This pin can also be used as an in-system power detect where an internal EDID can be powered from a 5 V signal of the HDMI port when it is connected to active equipment. This pin is 5 V tolerant. 99 PGND Ground PVDD Ground. 100 PVDD Power PLL Supply Voltage (1.8 V). 101 XTAL Miscellaneous analog Input Pin for 28.63636 MHz Crystal or an External 1.8 V 28.63636 MHz Clock Oscillator Source to Clock the ADV3014. AVR 2650 AVR 2650 harman/kardonharman/kardon 139 ADI Confidential ADV3014 Rev. Sp0 | Page 11 of 16 Pin No. Mnemonic Type Description 102 XTAL1 Miscellaneous analog Crystal Output Pin. This pin should be left floating if a clock oscillator is used. 103 PVDD Power PLL Supply Voltage (1.8 V). 104 PGND Ground PVDD Ground. 105 HP_CTRLA Digital output Hot Plug Control Output for Port A. This pin is 5 V tolerant. 106 5V_DETA Digital input 5 V Detect Pin for Port A in the HDMI Interface. This pin is 5 V tolerant. 107 RTERM Miscellaneous analog This pin sets the internal termination resistance. A 500 resistor between this pin and ground should be used. 108 DDCA_SDA Digital I/O HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input/output that is 5 V tolerant. 109 DDCA_SCL Digital input HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant. 110 CVDD Power Receiver Comparator Supply Voltage (1.8 V). 111 CGND Ground TVDD and CVDD Ground. 112 RXA_C HDMI input Digital Input Clock Complement of Port A in the HDMI Interface. 113 RXA_C+ HDMI input Digital Input Clock True of Port A in the HDMI Interface. 114 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 115 RXA_0 HDMI input Digital Input Channel 0 Complement of Port A in the HDMI Interface. 116 RXA_0+ HDMI input Digital Input Channel 0 True of Port A in the HDMI Interface. 117 CGND Ground TVDD and CVDD Ground. 118 RXA_1 HDMI input Digital Input Channel 1 Complement of Port A in the HDMI Interface. 119 RXA_1+ HDMI input Digital Input Channel 1 True of Port A in the HDMI Interface. 120 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 121 RXA_2 HDMI input Digital Input Channel 2 Complement of Port A in the HDMI Interface. 122 RXA_2+ HDMI input Digital Input Channel 2 True of Port A in the HDMI Interface. 123 HP_CTRLB Digital output Hot Plug Control Output for Port B. This pin is 5 V tolerant. 124 5V_DETB Digital input 5 V Detect Pin for Port B in the HDMI Interface. This pin is 5 V tolerant. 125 DGND Ground DVDD Ground. 126 DVDD Power Digital Supply Voltage (1.8 V). 127 DDCB_SDA Digital I/O HDCP Slave Serial Data Port B. DDCB_SDA is a 3.3 V input/output that is 5 V tolerant. 128 DDCB_SCL Digital input HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant. 129 CVDD Power Receiver Comparator Supply Voltage (1.8 V). 130 CGND Ground TVDD and CVDD Ground. 131 RXB_C HDMI input Digital Input Clock Complement of Port B in the HDMI Interface. 132 RXB_C+ HDMI input Digital Input Clock True of Port B in the HDMI Interface. 133 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 134 RXB_0 HDMI input Digital Input Channel 0 Complement of Port B in the HDMI Interface. 135 RXB_0+ HDMI input Digital Input Channel 0 True of Port B in the HDMI Interface. 136 CGND Ground TVDD and CVDD Ground. 137 RXB_1 HDMI input Digital Input Channel 1 Complement of Port B in the HDMI Interface. 138 RXB_1+ HDMI input Digital Input Channel 1 True of Port B in the HDMI Interface. 139 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 140 RXB_2 HDMI input Digital Input Channel 2 Complement of Port B in the HDMI Interface. 141 RXB_2+ HDMI input Digital Input Channel 2 True of Port B in the HDMI Interface. 142 HP_CTRLC Digital output Hot Plug Control Output for Port C. This pin is 5 V tolerant. 143 5V_DETC Digital input 5 V Detect Pin for Port C in the HDMI Interface. This pin is 5 V tolerant. 144 DDCC_SDA Digital I/O HDCP Slave Serial D