Denon-DRAF107-rec-sm维修电路图 手册.pdf
D open drain; active low C_STARTUP35OStartup ramp requires a charging capacitor of 4.7 nF to AGND in BTL mode. FREQ_ADJ1214IPWM frame rate programming pin requires resistor to AGND GND7, 23, 24, 57, 589PGround GND_A48, 4938PPower ground for half-bridge A GND_B46, 4737PPower ground for half-bridge B GND_C34, 3530PPower ground for half-bridge C GND_D32, 3329PPower ground for half-bridge D GVDD_A55-PGate drive voltage supply requires 0.1 uF capacitor to GND_A GVDD_B56-PGate drive voltage supply requires 0.1 uF capacitor to GND_B GVDD_C25-PGate drive voltage supply requires 0.1 uF capacitor to GND_C GVDD_D26-PGate drive voltage supply requires 0.1 uF capacitor to GND_D GVDD_AB-44PGate drive voltage supply requires 0.22 uF capacitor to GND_A/GND_B GVDD_CD-23PGate drive voltage supply requires 0.22 uF capacitor to GND_C/GND_D INPUT_A46IInput signal for half bridge A INPUT_B57IInput signal for half bridge B INPUT_C1012IInput signal for half bridge C INPUT_D1113IInput signal for half bridge D M12020IMode selection M22121IMode selection M32222IMode selection NC59-62-No connect, pins may be grounded. OC_ADJ13OAnalog over current programming pin requires resistor to ground. OSC_IO+1315I/OOscillaotor master/slave output/input. OSC_IO-1416I/OOscillaotor master/slave output/input. /OTW-18OOvertemperature warning signal, open drain, active low. /OTW116-OOvertemperature warning signal, open drain, active low. /OTW217-OOvertemperature warning signal, open drain, active low. OUT_A52, 5339, 40OOutput, half bridge A OUT_B44, 4536OOutput, half bridge B OUT_C36, 3731OOutput, half bridge C OUT_D28, 2927, 28OOutput, half bridge D PSU_REF631PPSU Reference requires close decoupling of 330 pF to AGND PVDD_A50, 5141, 42P Power supply input for half bridges A requires close decoupling of 2.2-uF capacitor to GND_A PVDD_B42, 4335P Power supply input for half bridges B requires close decoupling of 2.2-uF capacitor to GND_B PVDD_C38, 3932P Power supply input for half bridges C requires close decoupling of 2.2-uF capacitor to GND_C PVDD_D30, 3125, 26P Power supply input for half bridges D requires close decoupling of 2.2-uF capacitor to GND_D READY1919ONormal operation; open drain; active high /RESET24IDevice reset Input; active low, requires 47kOhm pull up resistor to VREG. /SD1517OShutdown signal, open drain, active low VDD642P Power supply for internal voltage regulator requires a 10-uF capacitor in parallel with a 0.1-uF capacitor to GND for decoupling. VI_CM68O Analog comparator reference node requires close decoupling of 1 nF to AGND VREG911PInternal regulator supply filter pin requires 0.1-uF capacitor to AGND (1)I = input, O = output, P = power RadioFans.CN 27 DRA-F107 / DRA-F107DAB ICE2QS01 (IC93) PinSymbolFunction 1ZCZero Crossing 2REGRegulation 3CSPrimary Current Sensing 4, 5HVHigh Voltage input 6OUTgate driver output 7VCCIC supply voltage 8GNDCommon ground 1 6 7 8 4 3 2 5 GNDZC REG CS VCC OUT HVHV Blockdigram GND 8 CS 3 REG 2 OUT 6 ZC 1 controller Vos OLP VCC OVP VCC UVP output OVP current limitation / foldback correction V V V V auto restart latch off current measurement V SWP VREF R ZCT2 VCCOVP vccuvp OPOVP csSW v1 power management Reg Vcsth on/off FF gate driver PWM generator Zero-crossing counter up/down counter HV 4, 5 VCC 7 power cell VOLP active burst control ringing suppression time control VZCT1 RadioFans.CN 28 DRA-F107 / DRA-F107DAB ICE2QS01 Functional description Functional Description 3Functional Description 3.1VCC Pre-Charging and Typical VCC Voltage During Start-up In the controller ICE2QS01, a power cell is integrated. As shown in Figure 2, the power cell consists of a high voltage device and a controller, whereby the high voltage device is controlled by the controller. The power cell provides a pre-charging of the VCC capacitor till VCC voltage reaches the VCC turned-on threshold VVCCon and the IC begins to operate, while it may keep the VCC voltage at a constant value during burst mode operation when the output voltage is pulled down or the power from the auxiliary winding is not enough, or when the IC is latched off in certain protection mode. Once the mains input voltage is applied, a rectified voltage shows across the capacitor Cbus. The high voltage device provides a current to charge the VCC capacitor Cvcc. Before the VCC voltage reaches a certain value, the amplitude of the current through the high voltage device is only determined by its channel resistance and can be as high as several mA. After the VCC voltage is high enough, the controller controls the high voltage device so that a constant current around 1mA is provided to charge the VCC capacitor further, until the VCC voltage exceeds the turned-on threshold VVCCon. As shown as the time phase I in Figure 3, the VCC voltage increase near linearly. Figure 3VCC voltage at start up The time taking for the VCC pre-charging can then be approximately calculated as: 1 where IVCCcharge2 is the charging current from the power cell which is 1.05mA, typically. Exceeds the VCC voltage the turned-on threshold VVCCon of at time t1, the power cell is switched off, and the IC begins to operate with a soft-start. Due to power consumption of the IC and the fact that still no energy from the auxiliary winding to charge the VCC capacitor before the output voltage is built up, the VCC voltage drops (Phase II). Once the output voltage is high enough, the VCC capacitor receives then energy from the auxiliary winding from the time point t2on. The VCC then will reach a constant value depending on output load. Since there is a VCC undervoltage protection, the capacitance of the VCC capacitor should be selected to be high enough to ensure that enough energy is stored in the VCC capacitor so that the VCC voltage will never touch the VCC under voltage protection threshold VVCCUVP before the output voltage is built up. Therefore, the capacitance should fulfill the following requirement: 2 with IVCCop the operating current of the controller. 3.2Soft-start At the time t1, the IC begins to operate with a soft-start. By this soft-start the switching stresses for the switch, diode and transformer are minimised. The soft-start implemented in the ICE2QS01 is a digital time-based function. The preset soft-start time is 24ms with 8 steps. The internal reference for the regulation voltage begins at 1.35V and with an increment of 0.35V for each following step. 3.3Normal Operation The PWM section of the IC can be divided into two main portions: PWM controller for normal operation and PWM controller for burst mode operation. The PWM controller for normal operation will be described in the following paragraphs, while the PWM controller for burst mode operation will be discussed in the next section. The PWM controller for normal operation consists of digital signal processing circuit including an up/down counter, a zero-crossing counter (ZC-counter) and a comparator, and analog circuit including a current measurement unit and a comparator. The switch-on and -off time point is determined by the digital circuit and the analog circuit, respectively. As input information for the switch-on determination, the zero- crossing input signal and the value of the up/down counter are needed, while the feedback signal vREG and the current sensing signal vCS are necessary for the switch-off determination. Details about the operation of the PWM controller in normal operation are illustrated in the following paragraphs. 3.3.1Switch-on Determination As mentioned above, the digital signal processing circuit consists of an up/down counter, a zero-crossing counter and a comparator. A ringing suppression time VVCCon VCC VVCCUVP t1tt2 iiiiii t1 VVCConCvcc? IVCCch e2arg - -= Cvcc IVCCopt2t1? VVCConVVCCUVP - -? RadioFans.CN 29 DRA-F107 / DRA-F107DAB Functional Description controller is implemented to avoid mistriggering by the ring after MOSFET is turned off. Functionality of these parts is described as in the following. 3.3.1.1Up/down Counter The up/down counter stores the number of zero crossing to be ignored before the main power switch is switched on after demagnetisation of the transformer. This value is a function of the regulation voltage, which contains information about the output power. Generally, a high output power results in a high regulation voltage. According to this information, the value in the up/down counter is changed to a low value in case of high regulation voltage, and to a high value in case of low regulation voltage. In ICE2QS01, the lowest value of the counter is 1 and the highest 7. Following text explains how the up/down counter value changes in responding to the regulation voltage vREG. The regulation voltage vREG is internally compared with three thresholds VRL, VRH and VRM. According to the results, the value in the up/down counter is changed, which is summarised in Table 1 and Figure 4 respectively. Table 1Operation of the up/down counter Figure 4Up/down counter operation According to the comparison results the up/down counter counts upwards, keeps unchanged or counts downwards. However, the value in up/down counter is limited between 1 and 7. If the counter tends to count beyond this range, the attempt is ignored. In normal case, the up/down counter can only be changed by one each time at the clock period of 48ms. However, to ensure a fast response to sudden load increase, the counter is set to 1 in the following switching period after the regulation voltage vREG exceeds the threshold VRM. 3.3.1.2Zero-Crossing Counter and Ringing Suppression Time Controller In the system, the voltage from the auxiliary winding is applied to the zero-crossing pin through a RC network, which provides a time delay to the voltage from the auxiliary winding. Internally, this pin is connected to a clamping network, a zero-crossing detector, an output overvoltage (OP OVP) detector and a ringing suppression time controller. During on-state of the power switch a negative voltage applies to the ZC pin. Through the internal clamping network, the voltage at the pin is clamped to certain level. However, it is highly recommended that a fast- recovery diode Dzc is added to block the negative voltage when the power switch is on. This is because the device in MOS technology is sensitive to negative voltage. The voltage at the ZC pin vZC is compared with the threshold VZCT1. Once the voltage vZC crosses the threshold at its falling edge, a pulse is generated which is fed to the zero-crossing counter and the counter value increases by 1. After MOSFET is turned on, there will be some oscillation on VDS, which will also appear on the voltage on ZC pin. To avoid the MOSFET is turned on mistriggerred by such oscillation, a ringing suppression timer is implemented. The time is dependent on the voltage vZC. When the voltage vZC is lower than the threshold VZCT2, a longer preset time applies, while a shorter time is set when the voltage vZC is higher than the threshold. The voltage vZC is used for the output overvoltage protection, as well. Once the voltage at this pin is higher than the threshold VOPOVP during off-time of the main switch, the IC is latched off after a fixed blanking time. To achieve the switch-on at voltage valley, the voltage from the auxiliary winding is fed to a time delay network (the RC network consists of Dzc, Rzc1, Rzc2 and Czcas shown in typical application circuit) before it is applied to the zero-crossing detector through the ZC pin. The needed time delay to the main oscillation signal ?t should be approximately one fourth of the oscillation period (by transformer primary inductor and drain- source capacitor) minus the propagation delay from the vREG up/down counter action Always lower than VRL Count upwards till 7 Once higher than VRL, but always lower than VRH Stop counting, no value changing Once higher than VRH, but always lower than VRM Count downwards till 1 Once higher than VRM Set up/down counter to 1 1Case 3 Case 2 Case 1 n n+1 n+2 n+2 n+2 n+2 n+1 n n-1 4 5 6 6 6 6 5 4 3 1 1 2 3 4 4 4 4 3 2 1 7 7 7 7 7 7 6 5 4 t t VFB VRM VRH VRL clockT=48ms 1 RadioFans.CN 30 DRA-F107 / DRA-F107DAB Functional Description detected zero-crossing to the switch-on of the main switch tdelay, theoretically: 3 This time delay should be matched by adjusting the time constant of the RC network which is calculated as: 4 3.3.1.3Switch-on Determination In the system, turn-on of the power switch depends on the value of the up/down counter, the value of the zero- crossing counter and the voltage at the ZC pin vZC. Turn-on happens only when the value in the both counters are the same and the voltage at the ZC is lower than the threshold VZCT1. For comparison of the values from both counters, a digital comparator is used. Once these counters have the same value, the comparator generates a signal which sets the on/off flip-flop, only when the voltage vZC is lower than the threshold VZCT1. Another signal which may trigger the digital comparator is the output of a TsMax clock signal, which limits the maximum off time to avoid the low-frequency operation. During active burst mode operation, the digital comparator is disabled and no pulse will be generated. 3.3.2Switch-off Determination In the converter system, the primary current is sensed by an external shunt resistor, which is connected between low-side terminal of the main power switch and the common ground. The sensed voltage across the shunt resistor vCS is applied to an internal current measurement unit, and its output voltage v1 is compared with the regulation voltage vreg. Once the voltage v1exceeds the voltage vREG, the output flip-flop is reset. As a result, the main power switch is switched off. The relationship between the v1 and the vcs is described by: 5 To avoid mistriggering caused by the voltage spike across the shunt resistor after switch-on of the main power switch, a 330ns leading edge blanking time applies to output of the comparator. 3.3.3Foldback Point Correction In addition to the cycle-by-cylce primary current limitation, the IC incorporats a foldback point correction. The current limit on CS pin voltage is now a time dependent one. If the mains input voltage is high, the MOSFET on time will be short and the current limit will be low. In such a way, the maximum output power for the SMPS designed with ICE2QS01 will be nearly constant against the variations of mains input voltage. The current sense voltage limit versus the MOSFET maximum on time is shown in Figure 5. ?t Tosc 4 - -tdelay= ?tdCzc Rzc1Rzc2? Rzc1Rzc2+ - -?= v13.3 vCS?0.7+= Figure 5 Maximum current limit versus MOSFET maximum on time 0 0.2 0.4 0.6 0.8 1 051015202530 Ton(us) Vcs-max(V) RadioFans.CN 31 DRA-F107 / DRA-F107DAB Functional Description 3.4Active Burst Mode Operation At very low load condition, the IC enters active burst mode opera
