Denon-AVR1712-avr-sm维修电路图 手册.pdf

D supports TMDS logic level. 48 TXC+ HDMI output Diferential Clock Output. Diferential clock output at the TMDS clock rate; supports TMDS logic level. 49 TXGND Ground TXAVDD Ground. 50 TX0 HDMI output Diferential Output Channel 0 Complement. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 51 TX0+ HDMI output Diferential Output Channel 0 True. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 52 TXGND Ground TXAVDD Ground. 53 TX1 HDMI output Diferential Output Channel 1 Complement. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 54 TX1+ HDMI output Diferential Output Channel 1 True. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 55 TXAVDD Power 1.8 V Power Supply for TMDS Outputs. RadioFans.CN 121 Pin No. Mnemonic Type Description 13 RXC_2 HDMI input Digital Input Channel 2 Complement of Port C in the HDMI Interface. 14 RXC_2+ HDMI input Digital Input Channel 2 True of Port C in the HDMI Interface. 15 HP_CTRLD Digital output Hot Plug Detect for Port D. 16 5V_DETD Digital input 5 V Detect Pin for Port D in the HDMI Interface. 17 DGND Ground DVDD Ground. 18 DVDD Power Digital Supply Voltage (1.8 V). 19 DDCD_SDA Digital I/O HDCP Slave Serial Data Port D. DDCD_SDA is a 3.3 V input/output that is 5 V tolerant. 20 DDCD_SCL Digital input HDCP Slave Serial Clock Port D. DDCD_SCL is a 3.3 V input that is 5 V tolerant. 21 CVDD Power Receiver Comparator Supply Voltage (1.8 V). 22 CGND Ground TVDD and CVDD Ground. 23 RXD_C HDMI input Digital Input Clock Complement of Port D in the HDMI Interface. 24 RXD_C+ HDMI input Digital Input Clock True of Port D in the HDMI Interface. 25 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 26 RXD_0 HDMI input Digital Input Channel 0 Complement of Port D in the HDMI Interface. 27 RXD_0+ HDMI input Digital Input Channel 0 True of Port D in the HDMI Interface. 28 CGND Ground TVDD and CVDD Ground. 29 RXD_1 HDMI input Digital Input Channel 1 Complement of Port D in the HDMI Interface. 30 RXD_1+ HDMI input Digital Input Channel 1 True of Port D in the HDMI Interface. 31 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 32 RXD_2 HDMI input Digital Input Channel 2 Complement of Port D in the HDMI Interface. 33 RXD_2+ HDMI input Digital Input Channel 2 True of Port D in the HDMI Interface. 34 CVDD Power Receiver Comparator Supply Voltage (1.8 V). 35 CGND Ground TVDD and CVDD Ground. 36 TXPVDD Power 1.8 V Power Supply for Digital and I/O Power Supply. This pin supplies power to the digital logic and I/Os. It should be fltered and as quiet as possible. 37 TXPLVDD Power 1.8 V Power Supply. 38 TXGND Ground TXPVDD Ground. 39 TXPGND Ground TXPLVDD Ground. 40 EXT_SWING Analog input This pin sets the internal reference currents. Place an 887 resistor (1% tolerance) between this pin and ground. 41 HPD_ARC Analog input Hot Plug Detect Signal. This pin indicates to the interface whether the receiver is connected. It supports 1.8 V to 5 V CMOS logic levels. 42 ARC+ Analog input Audio Return Channel Input (5 V Tolerant). 43 TXDDC_SDA Digital I/O Serial Port Data I/O to Receiver. This pin serves as the master to the DDC bus. It supports a 5 V CMOS logic level. 44 TXDDC_SCL Digital output Serial Port Data Clock to Receiver. This pin serves as the master clock for the DDC bus. It supports a 5 V CMOS logic level. 45 TXAVDD Power 1.8 V Power Supply for TMDS Outputs. 46 TXGND Ground TXAVDD Ground. 47 TXC HDMI output Diferential Clock Output. Diferential clock output at the TMDS clock rate; supports TMDS logic level. 48 TXC+ HDMI output Diferential Clock Output. Diferential clock output at the TMDS clock rate; supports TMDS logic level. 49 TXGND Ground TXAVDD Ground. 50 TX0 HDMI output Diferential Output Channel 0 Complement. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 51 TX0+ HDMI output Diferential Output Channel 0 True. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 52 TXGND Ground TXAVDD Ground. 53 TX1 HDMI output Diferential Output Channel 1 Complement. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 54 TX1+ HDMI output Diferential Output Channel 1 True. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 55 TXAVDD Power 1.8 V Power Supply for TMDS Outputs. RadioFans.CN 122 Pin No. Mnemonic Type Description 99 PGND Ground PVDD Ground. 100 PVDD Power PLL Supply Voltage (1.8 V). 101 XTAL Miscellaneous analog Input pin for 28.63636 MHz crystal or an external 1.8 V 28.63636 MHz clock oscillator source to clock the ADV7623. 102 XTAL1 Miscellaneous analog Crystal Output Pin. This pin should be left foating if a clock oscillator is used. 103 PVDD Power PLL Supply Voltage (1.8 V). 104 PGND Ground PVDD Ground. 105 HP_CTRLA Digital output Hot Plug Detect for Port A. 106 5V_DETA Digital input 5 V Detect Pin for Port A in the HDMI Interface. 107 RTERM Miscellaneous analog This pin sets the internal termination resistance. A 500 resistor between this pin and ground should be used. 108 DDCA_SDA Digital I/O HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input/output that is 5 V tolerant. 109 DDCA_SCL Digital input HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant. 110 CVDD Power Receiver Comparator Supply Voltage (1.8 V). 111 CGND Ground TVDD and CVDD Ground. 112 RXA_C HDMI input Digital Input Clock Complement of Port A in the HDMI Interface. 113 RXA_C+ HDMI input Digital Input Clock True of Port A in the HDMI Interface. 114 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 115 RXA_0 HDMI input Digital Input Channel 0 Complement of Port A in the HDMI Interface. 116 RXA_0+ HDMI input Digital Input Channel 0 True of Port A in the HDMI Interface. 117 CGND Ground TVDD and CVDD Ground. 118 RXA_1 HDMI input Digital Input Channel 1 Complement of Port A in the HDMI Interface. 119 RXA_1+ HDMI input Digital Input Channel 1 True of Port A in the HDMI Interface. 120 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 121 RXA_2 HDMI input Digital Input Channel 2 Complement of Port A in the HDMI Interface. 122 RXA_2+ HDMI input Digital Input Channel 2 True of Port A in the HDMI Interface. 123 HP_CTRLB Digital output Hot Plug Detect for Port B. 124 5V_DETB Digital input 5 V Detect Pin for Port B in the HDMI Interface. 125 DGND Ground DVDD Ground. 126 DVDD Power Digital Supply Voltage (1.8 V). 127 DDCB_SDA Digital I/O HDCP Slave Serial Data Port B. DDCB_SDA is a 3.3 V input/output that is 5 V tolerant. 128 DDCB_SCL Digital input HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant. 129 CVDD Power Receiver Comparator Supply Voltage (1.8 V). 130 CGND Ground TVDD and CVDD Ground. 131 RXB_C HDMI input Digital Input Clock Complement of Port B in the HDMI Interface. 132 RXB_C+ HDMI input Digital Input Clock True of Port B in the HDMI Interface. 133 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 134 RXB_0 HDMI input Digital Input Channel 0 Complement of Port B in the HDMI Interface. 135 RXB_0+ HDMI input Digital Input Channel 0 True of Port B in the HDMI Interface. 136 CGND Ground TVDD and CVDD Ground. 137 RXB_1 HDMI input Digital Input Channel 1 Complement of Port B in the HDMI Interface. 138 RXB_1+ HDMI input Digital Input Channel 1 True of Port B in the HDMI Interface. 139 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 140 RXB_2 HDMI input Digital Input Channel 2 Complement of Port B in the HDMI Interface. 141 RXB_2+ HDMI input Digital Input Channel 2 True of Port B in the HDMI Interface. 142 HP_CTRLC Digital output Hot Plug Detect for Port C. 143 5V_DETC Digital input 5 V Detect Pin for Port C in the HDMI Interface. 144 DDCC_SDA Digital I/O HDCP Slave Serial Data Port C. DDCC_SDA is a 3.3 V input/output that is 5 V tolerant. RadioFans.CN 123 ADV7623 Block diagram CH0 CH1 CH2 VIDEO DATA DE VS HS AUDIO DATA VIDEO DATA DE VS HS AUDIO DATA VIDEO DATA DE VS HS AUDIO DATA VIDEO DATA DE VS HS AUDIO DATA XTAL XTAL1 RXA_C RXB_C RXC_C RXD_C RXA_0 RXA_1 RXA_2 VIDEO/AUDIO CLOCK GENERATION RX PLL CEC TXC TX0 TX1 TX2 5V DETECT COMPONENT PROCESSOR SCL SDATA ALSB CS I2C CONTROLLER PWRDN RESET GLOBAL CONTROLS DDCA_SDA DDCA_SCL DDCB_SDA DDCB_SCL DDCC_SDA DDCC_SCL DDCD_SDA DDCD_SCL AP0_IN AP1_IN AP2_IN AP3_IN AP4_IN AP5_IN SCLK_IN MCLK_IN AP0_OUT AP1_OUT AP2_OUT AP3_OUT AP4_OUT AP5_OUT SCLK_OUT MCLK_OUT ARC+ RX EDID/ REPEATER CONTROLLER RX HPD CONTROLLER EP_MISO EP_MOSI EP_CS EP_SCK SPI MASTER/ SLAVE EQUALIZER RXB_0 RXB_1 RXB_2 EQUALIZER SAMPLER SAMPLER RXC_0 RXC_1 RXC_2 EQUALIZERSAMPLER RXD_0 RXD_1 RXD_2 EQUALIZER CEC CONTROLLER EDID RAM SAMPLER HDMI RECEIVER PROCESSOR TRANSMITTER PACKET BUILDER HDCP ENCRYPTION ENGINE HDMI ENCODER SERIALIZER TMDS DRIVERS INT1 INT2 INT_TX INTERRUPT CONTROLLER TXDDC_SDA TXDDC_SCL TX EDID/HDCP CONTROLLER EDID/HDCP BUFFER HPD_ARC TX HPD CONTROLLER HDCP DECRYPTION ENGINE SYNC MEASUREMENT PACKET PROCESSOR INFOFRAME PACKET MEMORY AUDIO PROCESSOR ARC RECEIVER AUDIO CAPTURE HDCP KEYS TX PLL ADV7623 5V_DETA 5V_DETB 5V_DETC 5V_DETD HP_CTRLA HP_CTRLB HP_CTRLC HP_CTRLD OSD RadioFans.CN 124 LC89058W-E(HDMI:IC21) Pin Functions no i t cnuF O/ I emaN .oN n iP 1 RXOUT1 O RX0-6 input S/PDIF through output pin 1 2 RX0 I5(pd) 5V withstand voltage TTL input level compatible S/PDIF input pin (connected to GND when RX1 is set) 3 RX1 I(pd) Co-axial compatible S/PDIF input pin (supported demodulation sampling frequency of up to 96kHz) 4 RX2 I5(pd) 5V withstand voltage TTL input level compatible S/PDIF input pin (connected to GND when RX1 is set) 5 RX3 I5(pd) 5V withstand voltage TTL input level compatible S/PDIF input pin 6 DGND Digital GND 7 DVDD Digital power supply (3.3V) 8 RX4 I5(pd) 5V tolerable TTL input level compatible S/PDIF input pin 9 RX5 I5(pd) 5V tolerable TTL input level compatible S/PDIF input pin 10 RX6 I5(pd) 5V tolerable TTL input level compatible S/PDIF input pin 11 DVDD Digital power supply (3.3V) 12 DGND Digital GND 13 LPF O PLL loop filter connection pin 14 AVDD Analog power supply (3.3V) 15 AGND Analog GND 16 RMCK O R system clock output pin (VCO, 512fs, XIN) 17 RBCK O/I R system bit clock I/O pin (64fs) 18 DGND Digital GND 19 DVDD Digital power supply (3.3V) 20 RLRCK O/I R system LR clock I/O pin (fs) 21 RDATA O Serial audio data output pin 22 SBCK O S system bit clock output pin (16fs, 32fs, 64fs, 128fs) 23 SLRCK O S system LR clock output pin (fs/4, fs/2, fs, 2fs) 24 SDIN I5 External serial audio data input pin MOUT 39 38 37 DI RERR SLRCK SDINDO 36 42 41 40 45 44 43 48 47 46 CL CE DGND XMODE GPIO0 DVDD GPIO2 GPIO1 RXOUT2 GPIO3 INT 35 CKST 34 AUDIO 333231 LC89058W-E DVDD 30 XIN 29 DGND 2827 DVDD 26 DVDD DGNDDGND 25 XOUT XMCK 23 24 21 RDATA SBCK DVDD RLRCK RBCK DGND AGND RMCK LPF AVDD * RX5 * RX6 DVDD * RX4 * RX3 DGND * RX1 * RX2 RXOUT1 * RX0 4365871091211 21 22 19 20 17 18 15 16 13 14 * : Pull-down resistor internal at no selection RadioFans.CN 125 LC89058W-EBlockdiagram LC89058W-E No.A1056-4/64 Continued from preceding page. Pin No. Name I/O Function 25 DGND Digital GND 26 DVDD Digital power supply (3.3V) 27 XMCK O Oscillation amplifier clock output pin 28 XOUT O Output pin connected to the resonator 29 XIN I External clock input pin, connected to the resonator (12.288MHz/24.576MHz) 30 DVDD Digital power supply 31 DGND Digital GND 32 MOUT I/O Emphasis information | Input fs monitor output | Chip address setting input pin 33AUDIO I/O Channel status bit 1 output | Chip address setting input pin 34 CKST I/O Clock switching transition period signal output | Master/slave setting input pin 35 INT I/O Microcontroller interrupt signal output | Pins44-48 I/O setting input pin 36 RERR O PLL lock error, data error flag output pin 37 DO O CCB microcontroller I/F, read data output pin (3-state) 38 DI I5 CCB microcontroller I/F, write data input pin 39 CE I5 CCB microcontroller I/F, chip enable input pin 40 CL I5 CCB microcontroller I/F, clock input pin 41 XMODE I5 System reset input pin 42 DGND Digital GND 43 DVDD Digital power supply (3.3V) 44 GPIO0 O/I General-purpose I/O pin | Selector input pin (output referred to RDATA pin) 45 GPIO1 O/I General-purpose I/O pin | Selector input pin (output referred to RLRCK pin) 46 GPIO2 O/I General-purpose I/O pin | Selector input pin (output referred to RBCK pin) 47 GPIO3 O/I General-purpose I/O pin | Selector input pin (output referred to RMCK pin) 48 RXOUT2 O RX0-6 input S/PDIF through output pin 2 * Input voltage: I= -0.3 to 3.6V, I5= -0.3 to 5.5V * Output voltage: O= -0.3 to 3.6V * Pins 2, 4, 5, 8, 9, 10, 24, 38, 39, 40, and 41 have an internal pull-down resistor (pd). Their level is fixed when they are unselected. * Pins 32 and 33 are input pins for chip address setting when pin 41 is held at the low level. * Pin 34 serves as the input pin for designating as the master or slave when pin 41 is held at the low level. * Pin 35 serves as the input pin for configuring the I/O of pins 44 to 47 when pin 41 is held at the low level. * The DVDD and AVDD pins must be held at the same level and turned on and off at the same timing to preclude Latch-up conditions. LC89058W-E No.A1056-5/64 6. Block Diagram Figure 6.1 LC89058W-E Block Diagram Microcontroller I/F 3533 Cbit, Pc 41 INT AUDIO Demodulation This is not a final specification. Some parametric limits are subject to change. 2 / 18 CONFIDENTIAL R2A15220FP-87D BLOCK DIAGRAM AND PIN CONFIGURATION (TOP VIEW) AGND SWC SLC INLB/RECL2 INRB/RECR2 INR11/RECR5 INL10/RECL4 RECR3 INL11/RECL5 FLIN1 RECL3 CIN1 FRIN1 SLIN1 SWIN1 AVEE MUTE FLIN2 FRIN2 SLIN2 SRIN2 CIN2 SWIN2 SBLIN2 SBRIN2 AVCC TREL BASSL1 BASSL2 FLOUT FLC FROUT AGND FRC ADCR SBLIN1 SRIN1 SBRIN1 SBL OUT ADCL SBR OUT SLOUT SBRC SROUT SWOUT SRC COUTINL5 INL1 INR1 INL2 INR2 INL3 INR3 INL4 INR4 INR5 INL6 INR6 INL7 INR7 INL8 INR8 INLA/RECL1 INRA/RECR1 INL9 INR9 SUBR1 SUBL1 INR10/RECR4 DATA CLOCK BASSR1 BASSR2 AGND AGND SBRCIN SBLCIN AGND SBLC FR Pre-OUT FL Pre-OUT SBR Pre-OUT TRER SUBR2 SUBL2 SRCIN SLCIN SR Pre-OUT SL Pre-OUT SBL Pre-OUT INR12 INL12 INR13 INL13 INR14 INL14 CC AGND DGND REC ATT 0/-6/-12/-18dB Bass/ Treble -14+14dB (2dB step) +42-95dB, -(0.5dBstep) +42-95dB, -(0.5dBstep) +42-95dB, -(0.5dBstep) +42-95dB, -(0.5dBstep) +42-95dB, -(0.5dBstep) +42-95dB, -(0.5dBstep) Tone +420dB (0.5dBstep) Tone Bass/ Treble -14+14dB (2dB step) 0-95dB, - (0.5dBstep) +420dB (0.5dBstep) 0-95dB, - (0.5dBstep) MCU I/F AVEE AVCC Bypass Tone Tone+MIX Bypass Tone Tone+MIX MAIN SUB MAIN SUB 81828384858687888990919293949596979899100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 5049484746454443424140393837363534333231 MAIN SUB1 SUB2 RadioFans.CN 140 R2A15218FPPinFuncti