Yamaha-TF-3-Service-Manual-Part-3电路原理图.pdf

91 TF5/TF3/TF1 PIN NO. I/OFUNCTIONNAME PIN NO. I/OFUNCTIONNAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 AIN2+ AIN2- GND VA REF_GND FILT+ VQ GND VA GND AIN4+ AIN4- AIN3+ AIN3- AIN7+ AIN7- AIN8+ AIN8- GND VX XTI XTO MCLK I I I I I O O I I I I I I I I I I I I I I/O I/O I/O Differential Analog Audio signals are presented differently to the delta sigma modulators via the AIN+/- pins. Ground Ground reference. Must be connected to analog ground. Analog Power Positive power supply for the analog section Reference Ground For the internal sampling circuits. Must be connected to analog ground. Positive Voltage Reference Reference voltage for internal sampling circuits. Quiescent Voltage Filter connection for the internal quiescent reference voltage. Ground Ground reference. Must be connected to analog ground. Analog Power Positive power supply for the analog section Ground Ground reference. Must be connected to analog ground. Differential Analog Audio signals are presented differently to the delta sigma modulators via the AIN+/- pins. Ground Ground reference. Must be connected to analog ground. Crystal Oscillator Power Also powers control logic to enable or disable oscillator circuits. Crystal Oscillator Connections I/O pins for an external crystal which may be used to generate MCLK. System Master Clock When a crystal is used, this pin acts as a buffered MCLK Source (Output). When the oscillator function is not used, this pin acts as an input for the system master clock. In this case, the XTI and XTO pins must be tied low. 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 LRCK/FS SCLK SDOUT4 SDOUT2 VLS GND SDOUT1 SDOUT3 GND VD CLKMODE VLC OVFL DIF1 DIF0 M1 M0 RST MDIV AIN6+ AIN6- AIN5+ AIN5- AIN1+ AIN1- I/O I/O O O I I O O I I I I O I I I I I I I I I I I I Serial Audio Channel Clock In I2S Mode, Serial Audio Channel Select. When low, the odd channels are selected. In LJ Mode, Serial Audio Channel Select. When high, the odd channels are selected. In TDM Mode, a frame sync signal. When high, it marks the beginning of a new frame of serial audio samples. In Slave Mode, this pin acts as an input pin. Main timing clock for the Serial Audio Interface During Master Mode, this pin acts as an output, and during Slave Mode it acts as an input pin. Serial Audio Data Channels 7,8. Serial Audio Data Channels 3,4. Serial Audio Interface Power Positive power for the serial audio interface. Ground Ground reference. Must be connected to analog ground. Serial Audio Data Channels 1,2. Serial Audio Data Channels 5,6. Ground Ground reference. Must be connected to analog ground. Digital Power Positive power supply for the digital section. CLKMODE Setting this pin HIGH places a divide-by-1.5 circuit in the MCLK path to the core device circuitry. Control Port Interface Power Positive power for the control port interface. Overflow Detects an overflow condition on both left and right channels. DIF1, DIF0 Inputs of the audio interface format. Mode Selection Determines the operational mode of the device. Reset The device enters a low power mode when low. MCLK Divider Setting this pin HIGH places a divide-by-2 circuit in the MCLK path to the core device circuitry. Differential Analog Audio signals are presented differently to the delta sigma modulators via the AIN+/- pins. CS5368-CQZR (X8488A00) ADC (Analog to Digital Converter) HAAD (HACOM): IC903 PIN NO. I/OFUNCTIONNAME PIN NO. I/OFUNCTIONNAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DVSS DVDD MCLK PDN BICK SDATA LRCK SMUTE/CSN DFS0/CAD0 DEM0/CCLK DEM1/CDTI DIF0 DIF1 DIF2 - - I I I I I I I I I I I I Digital ground Digital power supply +3.3 V Master clock input Power-down mode Audio serial data clock Audio serial data input L/R clock Soft mute/Chip select Sampling speed mode select/Chip address 0 De-emphasis enable 0/Control data clock De-emphasis enable 1/Control data input Digital input format 15 16 17 18 19 20 21 22 23 24 25 26 27 28 TTL VREFL VREFH AVDD AVSS AOUTR- AOUTR+ AOUTL- AOUTL+ VCOM P/S TST1/DZFL TST2/CAD1 ACKS/DZFR I I I - - O O O O O I O I I/O CMOS/TTL level select Low level voltage reference input High level voltage reference input Analog power supply +5 V Analog ground Rch negative analog output Rch positive analog output Lch negative analog output Lch positive analog output Common voltage output Parallel/serial select Test 1/Lch zero input detect Test 2/Chip address 1 Master clock auto setting mode/Rch zero input detect AK4396VF-E2 (X8324A00) DAC (Digital to Analog Converter)DA1 (DACOM): IC901 92 TF5/TF3/TF1 MAIN (MAINCOM): IC905 PIN NO. Outer No NameI/OFunction 1A1VSSGND GND 2A2VDD_MPU_MONIVoltage Monitor Input(Not Used) 3A3RESERVEDONot Used 4A4 OSC1_OUT OOSC1(for Internal RTC) Output 5A5VSS_RTCGND GND 6A6 OSC1_IN IOSC1(for Internal RTC) Input 7A7 AIN3 IA/D Input 8A8 AIN6 IA/D Input 9A9 VREFNIAnalog Negative Reference Input 10A10 NRESETIN_OUT BIDIRECTActive low Warm Reset 11A11 TDO OJTAG TEST DATA OUTPUT 12A12 TCK IJTAG TEST CLOCK 13A13 SPI1_SCLKBIDIRECTSPI Clock 14A14 GPIO321BIDIRECTGPIO 15A15 SPI1_CS1BIDIRECTSPI Chip Select 16A16 SPI0_CS0 BIDIRECTSPI Chip Select 17A17 SPI0_SCLK BIDIRECTSPI Clock 18A18VSSGND GND 19B1 DDR_A5 ODDR SDRAM ROW/COLUMN ADDRESS Output 20B2 DDR_WEN ODDR SDRAM WRITE ENABLE OUTPUT (ACTIVE LOW) 21B3 DDR_BA2 ODDR SDRAM BANK ADDRESS OUTPUT 22B4 ENZ_KALDO_1P8V IActive low enable input for internal CAP_VDD_RTC voltage regulator 23B5 RTC_PORZ IActive low RTC reset input 24B6 AIN0 IA/D Input 25B7 AIN2 IA/D Input 26B8 AIN5 IA/D Input 27B9 VREFPIAnalog Positive Reference Input 28B10 NTRST IJTAG TEST RESET (ACTIVE LOW) 29B11 TDI IJTAG TEST DATA INPUT 30B12 GPIO318BIDIRECTGPIO 31B13 SPI1_D0BIDIRECTSPI Data 32B14 EMU1 BIDIRECTMISC EMULATION PIN 33B15 PWRONRSTnIActive low Power on Reset 34B16 SPI0_D1 BIDIRECTSPI Data 35B17 SPI0_D0 BIDIRECTSPI Data 36B18 NNMI IExternal Interrupt to ARM Cortext A8 core 37C1 DDR_A9 ODDR SDRAM ROW/COLUMN ADDRESS Output 38C2 DDR_A4 ODDR SDRAM ROW/COLUMN ADDRESS Output 39C3 DDR_A3 ODDR SDRAM ROW/COLUMN ADDRESS Output 40C4 DDR_BA0 ODDR SDRAM BANK ADDRESS OUTPUT 41C5 EXT_WAKEUP IEXT_WAKEUP input 42C6 PMIC_POWER_EN OPMIC_POWER_EN output(Not Used) 43C7 AIN1 IA/D Input 44C8 AIN4 IA/D Input 45C9 AIN7 IA/D Input 46C10CAP_VBB_MPUVCC Cap for MPU Regulator 47C11 TMS IJTAG TEST MODE SELECT 48C12 GPIO317BIDIRECTGPIO 49C13 GPIO319BIDIRECTGPIO 50C14 EMU0 BIDIRECTMISC EMULATION PIN 51C15 SPI0_CS1 BIDIRECTSPI Chip Select 52C16 I2C0_SCL BIDIRECTI2C Clock 53C17 I2C0_SDA BIDIRECTI2C0 Data 54C18 GPIO07BIDIRECTGPIO 55D1 DDR_NCK ODDR SDRAM CLOCK OUTPUT (Differential-) 56D2 DDR_CK ODDR SDRAM CLOCK OUTPUT (Differential+) 57D3 DDR_A15 ODDR SDRAM ROW/COLUMN ADDRESS Output 58D4 DDR_A8 ODDR SDRAM ROW/COLUMN ADDRESS Output 59D5 DDR_A6 ODDR SDRAM ROW/COLUMN ADDRESS Output 60D6CAP_VDD_RTCVCC Cap for RTC 61D7 VDDS_RTCVCC VDDS for RTC 62D8 VDDA_ADCVCC VDDA for ADC 63D9CAP_VDD_SRAM_COREVCC Cap for SRAM Core VDD 64D10VDDS_SRAM_MPU_BBVCC VDDS for SRAM 65D11CAP_VDD_SRAM_MPUVCC Cap for VDD_SRAM_MPU 66D12 SPI1_D1BIDIRECTSPI Data 67D13 GPIO320BIDIRECTGPIO 68D14 GPIO020BIDIRECTGPIO 69D15 UART1_TXD BIDIRECTUART Transmit Data 70D16 UART1_RXD BIDIRECTUART Receive Data 71D17 I2C2_SCLBIDIRECTI2C Clock 72D18 I2C2_SDABIDIRECTI2C0 Data 73E1 DDR_BA1 ODDR SDRAM BANK ADDRESS OUTPUT 74E2 DDR_A7 ODDR SDRAM ROW/COLUMN ADDRESS Output 75E3 DDR_A12 ODDR SDRAM ROW/COLUMN ADDRESS Output 76E4 DDR_A2 ODDR SDRAM ROW/COLUMN ADDRESS Output 77E5VDDS_DDRVCC VDDS for DDR 78E6VDDSVCC VDDS 79E7VDDS_PLL_DDR VCC VDDS for DDR PLL 80E8 VSSA_ADCGND GND(for ADC) 81E9VDDS_SRAM_CORE_BGVCC VDDS for SRAM Core PIN NO. Outer No NameI/OFunction 82E10VDDSHV6VCC VDD for I/O 83E11VDDSHV6VCC VDD for I/O 84E12VDDSHV6VCC VDD for I/O 85E13VDDSHV6VCC VDD for I/O 86E14VDDSVCC VDDS 87E15 UART0_RXD BIDIRECTUART Receive Data 88E16 UART0_TXD BIDIRECTUART Transmit Data 89E17 I2C1_SCLBIDIRECTI2C Clock 90E18 I2C1_SDABIDIRECTI2C0 Data 91F1 DDR_CASN ODDR SDRAM COLUMN ADDRESS STROBE OUTPUT (ACTIVE LOW) 92F2 DDR_A11 ODDR SDRAM ROW/COLUMN ADDRESS Output 93F3 DDR_A0 ODDR SDRAM ROW/COLUMN ADDRESS Output 94F4 DDR_A10 ODDR SDRAM ROW/COLUMN ADDRESS Output 95F5VDDS_DDRVCC VDDS for DDR 96F6VDD_COREVCC VDD for Core 97F7VDD_COREVCC VDD for Core 98F8VSSGND GND 99F9VDDSVCC VDDS 100 F10VDD_MPUVCC VDD for MPU 101F11VDD_MPUVCC VDD for MPU 102 F12VDD_MPUVCC VDD for MPU 103 F13VDD_MPUVCC VDD for MPU 104 F14VDDSHV6VCC VDD for I/O 105 F15 USB1_DRVBUSBIDIRECTUSB1 DRVBUS 106 F16 USB0_DRVBUSBIDIRECTUSB0 DRVBUS 107 F17 GPIO226BIDIRECTGPIO 108 F18 GPIO227BIDIRECTGPIO 109G1 DDR_ODT OODT OUTPUT 110G2 DDR_RESETN OR3/DDR3L RESET OUTPUT(Not Used) 111G3 DDR_CKE ODDR SDRAM CLOCK ENABLE OUTPUT 112G4 DDR_RASN ODDR SDRAM ROW ADDRESS STROBE OUTPUT (ACTIVE LOW) 113G5VDDS_DDRVCC VDDS for DDR 114G6VDD_COREVCC VDD for Core 115G7VDD_COREVCC VDD for Core 116G8VSSGND GND 117G9VSSGND GND 118 G10VDD_COREVCC VDD for Core 119 G11VSSGND GND 120 G12VSSGND GND 121 G13VDD_MPUVCC VDD for MPU 122 G14VDDSHV6VCC VDD for I/O 123 G15 GPIO228BIDIRECTGPIO 124 G16 GPIO229BIDIRECTGPIO 125 G17 GPIO230BIDIRECTGPIO 126 G18 GPIO231BIDIRECTGPIO 127H1 DDR_A1 ODDR SDRAM ROW/COLUMN ADDRESS Output 128H2 DDR_CSN0 ODDR SDRAM CHIP SELECT OUTPUT 129H3 DDR_A13 ODDR SDRAM ROW/COLUMN ADDRESS Output 130H4 DDR_A14 ODDR SDRAM ROW/COLUMN ADDRESS Output 131H5VDDS_DDRVCC VDDS for DDR 132H6VSSGND GND 133H7VSSGND GND 134H8VSSGND GND 135H9VSSGND GND 136 H10VSSGND GND 137 H11VDD_COREVCC VDD for Core 138 H12VSSGND GND 139 H13VDD_MPUVCC VDD for Core 140 H14VDDSHV4VCC VDD for I/O 141 H15VDDS_PLL_MPUVCC VDDS for MPU PLL 142 H16 GPIO30BIDIRECTGPIO 143 H17 RMII1_CRS_DVBIDIRECTRMII Carrier Sense / Data Valid 144 H18 RMII1_REFCLK BIDIRECTRMII Reference Clock 145J1 DDR_D8 BIDIRECTDDR SDRAM DATA INPUT/OUTPUT 146J2 DDR_DQM1 ODDR WRITE ENABLE / DATA MASK FOR DATA15:8 147J3 DDR_VTP IVTP Compensation Resistor 148J4 DDR_VREF IVoltage Reference Input 149J5VDDS_DDRVCC VDDS for DDR 150J6VSSGND GND 151J7VSSGND GND 152J8VSSGND GND 153J9VSSGND GND 154J10VSSGND GND 155J11VSSGND GND 156 J12VDD_COREVCC VDD for Core 157 J13VDD_MPUVCC VDD for MPU 158 J14VDDSHV4VCC VDD for I/O 159 J15 RMII1_RXERBIDIRECTRMII Receive Data Error 160 J16 RMII1_TXENBIDIRECTRMII Transmit Enable 161 J17 GPIO34BIDIRECTGPIO 162 J18 UART4_RXDBIDIRECTUART Receive Data AM3352BZCZ60 (YF449B00) MICROPROCESSOR (MPU) 93 TF5/TF3/TF1 PIN NO. Outer No NameI/OFunction 163K1 DDR_D9 BIDIRECTDDR SDRAM DATA INPUT/OUTPUT 164K2 DDR_D10 BIDIRECTDDR SDRAM DATA INPUT/OUTPUT 165K3 DDR_D11 BIDIRECTDDR SDRAM DATA INPUT/OUTPUT 166K4 DDR_D12 BIDIRECTDDR SDRAM DATA INPUT/OUTPUT 167K5VDDS_DDRVCC VDDS for DDR 168K6VDD_COREVCC VDD for Core 169K7VSSGND GND 170K8VDD_COREVCC VDD for Core 171K9VSSGND GND 172 K10VSSGND GND 173 K11VSSGND GND 174 K12VDD_COREVCC VDD for Core 175 K13VDDSVCC VDDS 176 K14VDDSHV5VCC VDD for I/O 177 K15 UART4_TXDBIDIRECTUART Transmit Data 178 K16 RMII1_TXD1BIDIRECTRMII Transmit Data 179 K17 RMII1_TXD0BIDIRECTRMII Transmit Data 180 K18 UART2_RXDBIDIRECTUART Receive Data 181L1 DDR_DQS1 BIDIRECTDDR DATA STROBE FOR DATA15:8 (Differential+) 182L2 DDR_DQSN1 BIDIRECTDDR DATA STROBE FOR DATA15:8 (Differential-) 183L3 DDR_D13 BIDIRECTDDR SDRAM DATA INPUT/OUTPUT 184L4 DDR_D14 BIDIRECTDDR SDRAM DATA INPUT/OUTPUT 185L5VDDS_DDRVCC VDDS for DDR 186L6VDD_COREVCC VDD for Core 187L7VDD_COREVCC VDD for Core 188L8VDD_COREVCC VDD for Core 189L9VDD_COREVCC VDD for Core 190 L10VSSGND GND 191L11VSSGND GND 192 L12VSSGND GND 193 L13VSSGND GND 194 L14VDDSHV5VCC VDD for I/O 195 L15 RMII1_RXD1BIDIRECTRMII Receive Data 196 L16 UART3_TXDBIDIRECTUART Transmit Data 197 L17 UART3_RXDBIDIRECTUART Receive Data 198 L18 UART2_TXDBIDIRECTUART Transmit Data 199M1 DDR_D15 BIDIRECTDDR SDRAM DATA INPUT/OUTPUT 200M2 DDR_DQM0 ODDR WRITE ENABLE / DATA MASK FOR DATA7:0 201M3 DDR_D0 BIDIRECTDDR SDRAM DATA INPUT/OUTPUT 202M4 DDR_D1 BIDIRECTDDR SDRAM DATA INPUT/OUTPUT 203M5VPPNC (Not Used) 204M6VSSGND GND 205M7VSSGND GND 206M8VSSGND GND 207M9VSSGND GND 208 M10VSSGND GND 209 M11VDD_COREVCC VDD for Core 210 M12VSSGND GND 211 M13VDD_COREVCC VDD for Core 212 M14 VSSA_USBGND GND(for USB Analog) 213 M15 USB0_CE OUSB0 Active high Charger Enable output(Not Used) 214 M16 RMII1_RXD0BIDIRECTRMII Receive Data 215 M17 MDIO_DATA BIDIRECTMDIO Data 216 M18 MDIO_CLK OMDIO Clk 217N1 DDR_D2 BIDIRECTDDR SDRAM DATA INPUT/OUTPUT 218N2 DDR_D3 BIDIRECTDDR SDRAM DATA INPUT/OUTPUT 219N3 DDR_D4 BIDIRECTDDR SDRAM DATA INPUT/OUTPUT 220N4 DDR_D5 BIDIRECTDDR SDRAM DATA INPUT/OUTPUT 221N5VDDSHV6VCC VDD for I/O 222N6VDDSVCC VDDS 223N7VSSGND GND 224N8VDD_COREVCC VDD for Core 225N9VDD_COREVCC VDD for Core 226 N10VSSGND GND 227 N11VSSGND GND 228 N12VDD_COREVCC VDD for Core 229 N13VDD_COREVCC VDD for Core 230 N14 VSSA_USBGND GND(for USB Analog) 231 N15 VDDA3P3V_USB0VCC VDDA for USB0(3.3V) 232 N16 VDDA1P8V_USB0VCC VDDA for USB0(1.8V) 233 N17 USB0_DP BIDIRECTUSB0 Data plus 234 N18 USB0_DM BIDIRECTUSB0 Data minus 235P1 DDR_DQS0 BIDIRECTDDR DATA STROBE FOR DATA7:0 (Differential+) 236P2 DDR_DQSN0 BIDIRECTDDR DATA STROBE FOR DATA7:0 (Differential-) 237P3 DDR_D6 BIDIRECTDDR SDRAM DATA INPUT/OUTPUT 238P4 DDR_D7 BIDIRECTDDR SDRAM DATA INPUT/OUTPUT 239P5VDDSHV6VCC VDD for I/O 240P6VDDSHV6VCC VDD for I/O 241P7VDDSHV1VCC VDD for I/O 242P8VDDSHV1VCC VDD for I/O 243P9VDDSVCC VDDS PIN NO. Outer No NameI/OFunction 244 P10VDDSHV2VCC VDD for I/O 245 P11VDDSHV2VCC VDD for I/O 246 P12VDDSHV3VCC VDD for I/O 247 P13VDDSHV3VCC VDD for I/O 248 P14VDDSVCC VDDS 249 P15 USB0_VBUS IUSB0 VBUS 250 P16 USB0_ID IUSB0 OTG ID 251 P17 USB1_ID IUSB1 OTG ID (Not Used) 252 P18 USB1_CE OUSB1 Active high Charger Enable output (Not Used) 253R1 LCD_DATA0 / SYSBOOT0BIDIRECTLCD data bus/BOOT Mode Set 254R2 LCD_DATA1 / SYSBOOT1BIDIRECTLCD data bus/BOOT Mode Set 255R3 LCD_DATA2 / SYSBOOT2BIDIRECTLCD data bus/BOOT Mode Set 256R4 LCD_DATA3 / SYSBOOT3BIDIRECTLCD data bus/BOOT Mode Set 257R5 LCD HSYNC/GPIO223BIDIRECTGPIO 258R6 LCD_AC_BIAS_EN BIDIRECTLCD AC bias enable chip select 259R7 GPIO22BIDIRECTGPIO 260R8 MMC1_DAT2BIDIRECTMMC/SD/SDIO Data Bus 261R9 GPIO16BIDIRECTGPIO 262 R10VDDS_PLL_CORE_LCDVCC VDDS for LCD PLL 263 R11 VDDS_OSCVCC VDDS for OSC 264 R12 GPIO113BIDIRECTGPIO 265 R13 GPIO116BIDIRECTGPIO 266 R14 GPIO120BIDIRECTGPIO 267 R15 VDDA3P3V_USB1VCC VDDA for USB1(3.3V) 268 R16 VDDA1P8V_USB1VCC VDDA for USB1(1.8V) 269 R17 USB1_DP BIDIRECTUSB1 Data plus (Not Used) 270 R18 USB1_DM BIDIRECTUSB1 Data minus (Not Used) 271T1 LCD_DATA4 / SYSBOOT4BIDIRECTLCD data bus/BOOT Mode Set 272T2 LCD_DATA5 / SYSBOOT5BIDIRECTLCD data bus/BOOT Mode Set 273T3 LCD_DATA6 / SYSBOOT6BIDIRECTLCD data bus/BOOT Mode Set 274T4 LCD_DATA7 / SYSBOOT7BIDIRECTLCD data bus/BOOT Mode Set 275T5 LCD_DATA15 / SYSBOOT15BIDIRECTLCD data bus/BOOT Mode Set 276T6 GPIO25BIDIRECTGPIO 277T7 GPIO23BIDIRECTGPIO 278T8 MMC1_DAT3BIDIRECTMMC/SD/SDIO Data Bus 279T9 GPIO17BIDIRECTGPIO 280 T10 GPIO023BIDIRECTGPIO 281 T11 GPIO026BIDIRECTGPIO 282 T12 GPIO112BIDIRECTGPIO 283 T13 GPIO20BIDIRECTGPIO 284 T14 GPIO119BIDIRECTGPIO 285 T15 GPIO123BIDIRECTGPIO 286 T16 GPIO126BIDIRECTGPIO 287 T17 GPIO030BIDIRECTGPIO 288 T18 USB1_VBUS IUSB1 VBUS