Teac-CT-W2850-S1-Service-Manual电路原理图.pdf

SERVICE MANUAL CTW2850S1 16:19 CTV 11AK33 CHASSIS JUN03 SERVCTW2850S1 RadioFans.CN 收音机爱 好者资料库 11 AK-33 Service Manual RadioFans.CN 收音机爱 好者资料库 1.INTRODUCTION _4 2.SMALL SIGNAL PART WITH TDA8885 _4 2.1.Vision IF amplifier _ 4 2.2.Video Switches_ 5 2.3.Sound Circuit_ 5 2.4.Synchronisation circuit_ 5 2.5.Chroma and Luminance processing _ 6 2.6.Colour Decoder _ 6 2.7.PICTURE IMPROVEMENT FEATURES_ 7 2.8.RGB output circuit and black-current stabilisation_ 7 2.9.EAST WEST OUTPUT STAGE_ 8 3.TUNER_8 4.VIDEO SWITCH TEA6415C _9 5.MULTI STANDARD SOUND PROCESSOR_9 6.SOUND OUTPUT STAGE WITH TDA 7265_9 7.VERTICAL OUTPUT STAGE WITH STV 9379 _10 8.VIDEO OUTPUT AMPLIFIER TDA6108_10 9.COMBFILTER TDA 9181_10 10.POWER SUPPLY (SMPS) _10 11.POWER FACTOR CORRECTION _10 12.MICROCONTROLLER SDA555X _10 12.1.General Features _ 10 12.2.External Crystal and Programmable clock speed_ 10 12.3.Microcontroller Features _ 10 12.4.Memory _ 11 12.5.Display Features _ 11 12.6.ROM Characters_ 11 12.7.Acquisition Features _ 11 12.8.Ports _ 11 13.SERIAL ACCESS CMOS 8K (1024*8) EEPROM ST24C08 _12 14.CLASS AB STEREO HEADPHONE DRIVER TDA1308 _12 15.SAW FILTERS_12 16.IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM_12 16.1.TDA8885:_ 12 16.1.1.GENERAL DESCRIPTION _12 16.1.2.FEATURES_12 16.1.3.Pin Description _13 16.2.UV1315, UV1316 _ 15 16.2.1.General description of UV1315: _15 16.2.2.Features of UV1315:_15 16.2.3.General description of UV1316: _15 16.2.4.Features of UV1316:_15 16.3.TEA6415C:_ 16 16.3.1.General Description: _16 16.3.2.Features: _16 16.4.TDA7265:_ 17 16.4.1.Features: _17 16.4.2.Pinning:_17 16.5.TDA6108Q: _ 17 16.5.1.Features: _17 16.6.74 HCT 32 _ 18 16.6.1.PINNING _18 16.7.MC44608 _ 18 16.7.1.General description:_18 16.7.2.General Features _18 16.8.SDA5555: _ 19 16.8.1.General description:_19 16.9.TDA9181:_ 20 16.9.1.General Features:_20 16.9.2.Limits:_20 16.10.TCD1102:_ 21 16.10.1.Description _21 16.10.2.Applications _21 16.10.3.General features: _21 16.11.ST24C08: _ 21 16.11.1.General description:_21 16.11.2.Features: _21 16.12.TDA1308:_ 22 16.12.1.Features: _22 16.13.PCF8583: _ 22 16.13.1.FEATURES_22 16.13.2.GENERAL DESCRIPTION _23 16.14.MC33260:_ 23 16.14.1.General Features:_23 16.14.2.Safety Features:_23 16.14.3.LIMITS:_23 16.14.4.PINNING _23 16.15.STV9379: _ 24 16.15.1.DESCRIPTION_24 16.15.2.PINNING _24 16.16.MSP34XX :_ 24 MSP3410D _24 16.17.LM358N: _ 26 16.17.1.General Description_26 16.17.2.Unique Characteristics_26 16.17.3.Advantages _26 16.17.4.Features_26 17.AK33 CHASSIS MANUAL ADJUSTMENTS PROCEDURE _26 1. INTRODUCTION 11AK33 is a 110 chassis capable of driving 28-29”,32”,33” tubes at appropriate currents The chassis is a Frequency Controlled Tuning (PLL) and control system for multi-standard TV receivers with on- screen-display (OSD) for all relevant control functions. The system is based on the one-chip I2C bus controlled video processing / deflection IC TDA8885 which also controls sound. German stereo and Nicam is detected and processed by the MSP 3410 G. Dolby sound is processed by MSP 3452 G, virtual dolby by MSP 3411G, BTSC Stereo by MSP 3430G IC s by option. All sound processors also control the sound volume, balance, tone and spatial stereo effect. The user-interface is menu based control system with cursor keys. Only for some functions the colour keys are needed: This means that some of the functions can also be operated from the local keyboard (i.e. Vol -, Vol +, P -, P+ and M). Teletext is done by the microcontroller on-chip teletext module. 2. SMALL SIGNAL PART WITH TDA8885 The TDA8885 combine all small signal functions required for a colour TV receiver. 2.1. Vision IF amplifier The IF-amplifier contains 3 ac-coupled control stages with a total gain control range, which is higher then 66 dB. The sensitivity of the circuit is comparable. The video signal is demodulated by means of an alignment-free PLL carrier regenerator with an internal VCO. This VCO is calibrated by means of a digital control circuit, which uses the clock frequency of the m-Controller/Teletext decoder as a reference. The frequency setting for the various standards (33.4, 33.9, 38, 38.9, 45.75 and 58.75 MHz) is realised via the I 2 C-bus. To get a good performance for phase modulated carrier signals the control speed of the PLL can be increased by means of the FFI bit. The AFC output is generated by the digital control circuit of the IF-PLL demodulator and can be read via the I 2 C bus. For fast search tuning systems the window of the AFC can be increased with a factor 3. The setting is realised with the AFW bit. The AGC-detector operates on top sync and top white-level. The demodulation polarity is switched via the I 2 C-bus. The AGC detector capacitor is integrated. The time-constant can be chosen via the I 2 C-bus. The time-constant of the AGC system during positive modulation is rather long to avoid visible variations of the signal amplitude. To improve the speed of the AGC system a circuit has been included which detects whether the AGC detector is activated every frame period. When during 3 field periods no action is detected the speed of the system is increased. For signals without peak white information the system switches automatically to a gated black level AGC. Because a black level clamp pulse is required for this way of operation the circuit will only switch to black level AGC in the internal mode. The circuit contains a video identification circuit, which is independent of the synchronisation circuit. Therefore search tuning is possible when the display section of the receiver is used as a monitor. However, this Ident circuit cannot be made as sensitive as the slower sync Ident circuit (SL) and we use both Ident outputs to obtain a reliable search system. The Ident output is supplied to the tuning system via the I 2 C-bus. The input of the identification circuit is connected to pin 24, the internal CVBS input. This has the advantage that the Ident circuit can also be made operative when a scrambled signal is received (descrambler connected between the IF video output (pin 16) and pin 24). A second advantage is that the Ident circuit can be used when the IF amplifier is not used The video Ident circuit can also be used to identify the selected CBVS or Y/C signal. The switching between the 2 modes can be realised with the VIM bit. The IC contains a group delay correction circuit, which can be switched between the BG and a flat group delay response characteristic. This has the advantage that in multi-standard receivers no compromise has to be made for the choice of the SAW filter. Also the sound trap is integrated within the IC .The centre frequency of the trap can be switched via the I 2 C-bus. For mono- FM versions it is possible to obtain a demodulated IF video signal which has not passed the sound trap so that an external stereo decoder can be driven. This function is selected by means of the ICO bit (sub- address 28H). The signal is available on pin 27 (audio output pin when ICO = 0). The S/N ratio of the selected video signal can be read via the bits SN1/SN0 in sub-address 03H. 2.2. Video Switches The circuit has an input for the internal CVBS signal and 2 inputs for external CVBS or Y signals. The circuit has only 1 chroma input so that it is not possible to apply 2 separate Y/C inputs. The switch configuration is given in Fig. A. The selection of the various sources is made via the I 2 C-bus. The QFP-64 version has 2 independently switchable outputs. The CVBS1O output is identical to the selected signal that is supplied to the internal video processing circuit and can therefore be used as source signal for a teletext decoder. Both CVBS outputs have an amplitude of 2.0 VP-P . The CVBS2O output can for instance be used as drive signal for a PIP decoder. If the Y/C-3 signal is selected for one of the outputs the luminance and chrominance signals are added so that a CVBS signal is obtained again. 2.3. Sound Circuit The sound IF amplifier is similar to the vision IF amplifier and has a gain control range of about 66 dB. The AGC circuit is related to the SIF carrier levels (average level of AM or FM carriers) and ensures a constant signal amplitude of the AM demodulator and the QSS mixer. A multiplier realises the single reference QSS mixer. In this multiplier the SIF signal is converted to the intercarrier frequency by mixing it with the regenerated picture carrier from the VCO. The mixer output signal is supplied to the output via a high-pass filter for attenuation of the residual video signals. With this system a high performance hi-fi stereo sound processing can be achieved. To optimise the performance of the demodulator the offset can be compensated by means of an I 2 C-bus setting. The AM sound demodulator is realised by a multiplier. The modulated sound IF signal is multiplied in phase with the limited SIF signal. The demodulator output signal is supplied to the output via a low-pass filter for attenuation of the carrier harmonics. The AM signal is supplied to the output (pin 27) via the volume control. It is possible to get the AM output signal (not controlled on amplitude) on the QSS intercarrier output. The selection is made by means of the AM bit in sub-address 29H. Another possibility is that pin 11 can be used as external audio input pin and pin 49 can be used as (non-controlled) AM output pin. This can be realised by means of the setting the control bits CMB0 and CMB1 in sub-address 22H. 2.4. Synchronisation circuit The sync separator is preceded by a controlled amplifier, which adjusts the sync pulse amplitude to a fixed level. These pulses are fed to the slicing stage, which is operating at 50% of the amplitude. The separated sync pulses are fed to the first phase detector and to the coincidence detector. This coincidence detector is used to detect whether the line oscillator is synchronised with the incoming signal and can also be used for transmitter identification. This circuit can be made less sensitive by means of the STM bit. This mode can be used during search tuning to avoid that the tuning system will stop at very weak input signals. The first PLL has a very high statically steepness so that the phase of the picture is independent of the line frequency. The horizontal drive signal is generated by an internal VCO, which is running at a frequency of 25 MHz. This oscillator is stabilised to that frequency by using the 12 MHz frequency of the crystal oscillator as a reference. The time-constant of the first loop can be forced by the I 2 C-bus (fast or slow). If required the IC can select the time-constant depending on the noise content of the incoming video signal. The horizontal output signal is generated by means of a second loop, which compares the phase of the internal oscillator signal with the phase of the incoming