Kenwood-TK-285-Service-Manual电路原理图.pdf

VHF FM TRANSCEIVERTK-285/(N)© 2000-6 PRINTED IN JAPANB51-8530-00(S) 847SERVICE MANUALGENERAL . 2SYSTEM SET-UP . 2OPERATING FEATURES . 3REALIGNMENT . 4CIRCUIT DESCRIPTION . 6SEMICONDUCTOR DATA . 11DESCRIPTION OF COMPONENTS . 13PARTS LIST. 14EXPLODED VIEW . 22PACKING . 23ADJUSTMENT . 24TERMINAL FUNCTION . 32PC BOARD VIEWSDISPLAY UNIT (X54-3210-13) . 33TX-RX UNIT (X57-619X-XX) . 39SCHEMATIC DIAGRAM . 45BLOCK DIAGRAM . 49LEVEL DIAGRAM . 51OPTIONS . 52SPECIFICATIONS .BACK COVERCONTENTSCAUTIONWhen using an external power connector, please usewith maximum final module protection of 9V.Photo is K typeKnob (ENC)(K29-5232-03)Knob (VOL)(K29-5231-03)Cabinet assy(A02-2055-53)(16 keys)Badge(B43-1106-14)Packing(G53-0896-02)(16 keys)Panel assy(A62-0535-04)Helical antenna(T90-0733-05):K, E(T90-0734-05):(N)MKnob (PTT etc)(K29-5157-03)TK-285/(N)2GENERAL / SYSTEM SET-UPUnitModel 1) Switching between transmission and reception by PTTsignal input.2) Reading system, group, frequency, and program datafrom the memory circuit.3) Sending frequency program data to the PLL.4) Controlling squelch on/off by the DC voltage from thesquelch circuit.5) Controlling the audio mute circuit by decode data input.6) Transmitting tone and encode data.6-1. Memory circuitMemory circuit consists of the CPU (IC19) and a flashmemory (IC17).A flash memory has a capacity of 2M bits and contains thetransceiver control program for the CPU and the data foroperating features.This program can be easily downloaded from an externaldevice.lFlash MemoryNote : The flash memory stores the data containing the FPU(KPG-62D) program, Security Number (MPT Serial Number)and firmware program (User mode, Test mode, Tuning mode,etc.).This data must be reinstalled when replacing the flash memory.lEEPROMNote : The EEPROM stores tuning data (Deviation, Squelch,etc.)Realign the transceiver after replacing the EEPROM.Low battery warningThe red LED flashes duringtransmissionThe red LED flashes andcontinuous beep soundswhile PTT pressedBattery conditionThe battery voltage is low butthe transceiver is still usable.The battery voltage is low andthe transceiver is not usableto make calls.6-3. Key inputIf the clock is supplied to CLK terminal when the RESterminal (CPU pin 78) of the decade counter (IC301) is set toLow, Q0 to Q7 become High sequentially. Normally, KI1 andKI2 are Low (pulled down). When any key is pressed. KI1 orKI2 become High. The CPU detects which key is pressed,according to the voltage of KI1 and Kl2 and clock timing.Fig. 10 Key inputIC19CPUQ5Q1Q0Q2Q6Q7Q3VssVddRESCLKCLCAQ9Q4Q8KI1KI2CKKRSTIC30116 keysRESETCLOCKQ0Q1Q2Q3Q4Q5Q6Q7Q8Q9CLOCKINHIBITCARRYOUTFig. 11 Decade counter timing chartFig. 9 Memory circuitTK-285/(N)108. Power Supply CircuitBattery +B is supplied via a 3A fuse from the battery terminalconnected to the TX-RX unit. After passing through the powerswitch, power supply (SB) is applied to the three AVRs. IC5supplies 5V (5M) to the control circuit, and IC9 supplies 5V(5C) to common circuits. IC6 supplies to the TX circuit, the RXcircuit and common circuits of needless save mode. Duringtransmission, 5TC becomes Low and Q3 is turned ON to supply5V (5T) to the TX circuit. During reception, 5RC becomes Lowand Q2 is turned ON to supply 5V (5R) to the RX Circuit.Fig. 14 Power supply circuitFig. 13 DecodeIC4AMPIC13AF ICIC11LPFIC19CPUAFRDTLSDIN2195CIRCUIT DESCRIPTIONFig. 12 EncodeSUMSUMIC7(1/2)SUMR166 R162C176 C170 R1361LSDOUTHSDOUTIC19CPUO5O2O3O6I2I1I5IC8D/A (ADJ)VCOMDA1RX AudioMIC INIC132LPFIC10I6I3VCXOX1MBAFAMPIC7 (2/2)O1BUFFAMPIC17-2. DecodelLow-speed data (QT,DQT)The demodulated signal from the IF IC (IC12) is amplifiedby IC4 (2/2) and passes through a low-pass filter (IC11) toremove audio components. The signal is input to pin 95 of theCPU.The CPU digitizes this signal, performs processing such asDC restoration, and decodes the signal.lFFSKThe FFSK input signal from the IF IC is amplified by IC4(1/ 2) and goes to pin 5 of IC13. The signal is demodulated byFFSK demodulator in IC13. The demodulated data goes tothe CPU for processing.7. Signalling Circuit7-1. EncodelLow-speed data (QT,DQT)Low-speed data is output from pin 1 of the CPU. The signalpasses through a low-pass CR filter, and goes to the summingamplifier (IC7 1/2). The signal is mixed with the audio signaland goes to the VCO (A1) and VCXO (X1) modulation inputafter passing through the D/A converter (IC8) for BALadjustment.lHigh-speed data (DTMF)High-speed data (HSD) is output from pin 2 of the CPU.The signal passes through a low-pass filter consisting of IC10,and provides a TX HSD tone and a RX HSD tone. TX HSDdeviation making an adjustment by microprocessor is passedthrough the D/A convertor (IC8) and then applied to the audioprocessor (IC13).The signal is mixed with the audio signal and goes to theVCO and VCXO. The RX HSD tone is passed a summingamplifier (IC7 2/2). The D/A converter (IC8) for audio control,audio power amplifier and then to the speaker.lFFSKESN utilizes 1200bps FFSK signal. FFSK signal is outputfrom pin 6 of IC13. The signal passes through the D/A converter(IC8) for the FFSK deviation adjustment. and is routed to theVCO. When encoding FFSK, the microphone input signal ismuted.Display unitQ25RC5TC5R5T5CNSIC6IC9IC5Q3RF power amp (IC100)+BF1SBON/OFFVOL5M5C