Kenwood-TM-271-A-Service-Manual电路原理图.pdf

© 2003-10 PRINTED IN JAPANB51-8663-00 (N)743VHF FM TRANSCEIVERTM-271A/271ESERVICE MANUALCIRCUIT DESCRIPTION . 2SEMICONDUCTOR DATA . 8COMPONENTS DESCRIPTION . 9PARTS LIST . 10EXPLODED VIEW. 17PACKING . 18RESETTING THE TRANSCEIVER . 19ADJUSTMENT . 20TERMINAL FUNCTION . 27PC BOARDDISPLAY UNIT (X54-3450-10) . 28TX-RX UNIT (X57-685X-XX). 30SCHEMATIC DIAGRAM. 34BLOCK DIAGRAM . 38LEVEL DIAGRAM . 40SPECIFICATION . BACK COVERCONTENTSMicrophone(T91-0624-05)Cabinet(A01-2193-01)Panel assy(A62-1088-03)Knob (Encoder)(K29-9293-03)Knob (Volume)(K29-9292-03)Key top(K29-9291-01)Microphone(T91-0641-05)Cabinet(A01-2193-01)Panel assy(A62-1088-03)Knob (Encoder)(K29-9293-03)Knob (Volume)(K29-9292-03)Key top(K29-9291-01)TM-271A (M2,M4)TM-271A/E (K,M3,E)TM-271A/271E2Frequency ConfigurationThe receiver utilizes double conversion. The first IF is49.95MHz and the second IF is 450kHz. The first local oscil-lator signal is supplied from the PLL circuit.The PLL circuit in the transmitter generates the necessaryfrequencies. Figure 1 shows the frequencies.CIRCUIT DESCRIPTIONReceiver SystemThe receiver is double conversion superheterodyne. Thefrequency configuration is shown in Figure 1. Front-end RF AmplifierAn incoming signal from the antenna is applied to an RFamplifier (Q353) after passing through a transmit/receiveswitch circuit (D603, D605 are off) and a band pass filter(L357, L356 and varactor diodes : D353, D354). After thesignal is amplified (Q353), the signal is filtered through a bandpass filter (L354, L355 and varactor diodes: D351, D352) toeliminate unwanted signals before it is passed to the firstmixer.The voltage of these diodes are controlled by tracking theCPU (IC101) center frequency of the band pass filter. (SeeFig. 2.) First MixerThe signal from the RF amplifier is heterodyned with thefirst local oscillator signal from the PLL frequency synthesizercircuit at the first mixer (Q352) to create a 49.95MHz firstintermediate frequency (1st IF) signal. The first IF signal isthen fed through one pair of monolithic crystal filter (MCF :XF351) to further remove spurious signals.ANTSWRFAMP1stMIXAFPATCXOMICAMPX3multiplyRFAMPPOWERAMPCF 450kHzMCF49.95MHzIF SYSTEMPLL/VCO16.8MHz50.4MHzANTRXTXSPMIC1/2Fig. 1 Frequency configuration IF AmplifierThe first IF signal is amplified by Q351, and then goes toIC301 (FM processing IC). The signal is heterodyned againwith a second local oscillator signal within IC301 to create a450kHz second IF signal. The second IF signal is then fedthrough a 450kHz ceramic filter (Wide : CF301, Narrow :CF302) to further eliminate unwanted signals before it is am-plified and FM detected in IC301.Item RatingNominal center frequency 49.95MHzPass bandwidth ±5.0kHz or more at 3dB35dB stop bandwidth ±20.0kHz or lessRipple 1.0dB or lessInsertion loss 5.0dB or lessGuaranteed attenuation 80dB or more at fo±1MHzSpurious 40dB or moreTerminal impedance 350 / 5.5pFTable 1 Crystal filter (L71-0620-05) : XF351Item RatingNominal center frequency 450kHz6dB bandwidth ±6.0kHz or more50dB bandwidth ±12.5kHz or lessRipple 2.0dB or lessInsertion loss 6.0dB or lessGuaranteed attenuation 35.0dB or more within fo±100kHzTerminal impedance 2.0kTable 2 Ceramic filter (L72-0993-05) : CF301Item RatingNominal center frequency 450kHz6dB bandwidth ±4.5kHz or more50dB bandwidth ±10.0kHz or lessRipple 2.0dB or lessInsertion loss 6.0dB or lessGuaranteed attenuation 60.0dB or more within fo±100kHzTerminal impedance 2.0kTable 3 Ceramic filter (L72-0999-05) : CF302ANTL357,356D353,354BPFQ353RF AMPQ351IF AMPIC161D/A CONVERTERQ352MIXXF351MCFD602D603D605ANTSWIC161D/AIC203DC AMPQ302X3 multiplyIC4021/2 dividerX401TCXOIC301IF system1st local OSC (VCO/PLL)W/NO(EVOL2)CF301 (Wide)CF302 (Narrow)TVCPUL354,355D351,352BPFFig. 2 Receiver systemTM-271A/271E3 Wide/Narrow Switching CircuitThe Wide port (pin 65) and Narrow port (pin 64) of the CPUis used to switch between ceramic filters. When the Wideport is high, the ceramic filter SW diodes (D303, D302) causeCF301 to turn on to receive a Wide signal.When the Narrow port is high, the ceramic filter SW di-odes (D303, D302) cause CF302 to turn on to receive a Nar-row signal. (See Fig. 3.) AF Signal SystemThe detection signal from IF IC (IC301) goes to D/A con-verter (IC161) to adjust the gain and is output to AF filter(IC251) for characterizing the signal. The AF signal outputfrom IC251 and the DTMF signal, BEEP signal are summedand the resulting signal goes to the D/A converter (IC161).The AFO output level is adjusted by the D/A converter. Thesignal output from the D/A converter is input to the audiopower amplifier (IC252). The AF signal from IC252 switchesbetween the internal speaker and speaker jack (J1) output.(See Fig. 4.) Squelch CircuitThe detection output from the FM IF IC (IC301) passesthrough a noise amplifier (Q301) to detect noise. A voltage isapplied to the CPU (IC101). The CPU controls squelch ac-cording to the voltage (SQIN) level. The signal from the RSSIpin of IC301 is used for S-meter. The electric field strength ofthe receive signal can be known before the SQIN voltage isinput to the CPU, and the scan stop speed is improved.NarrowIC101 64pinIF_IN MIX_OIC301IF SystemCF302(Narrow)CF301(Wide)R320 R319R317R318D303 D302WideIC101 65pinAFFilterD/ACONV.D/ACONV.IC161 IC251 IC161W/NO(EVOL2)AF PAIC252 SPIF ICIC301Q301NOISE AMP D301IC301 IC101AFORSSIDETCPUIFSYSTEMSQINRSSIFig. 3 Wide/Narrow switching circuitFig. 4 AF signal systemFig. 5 Squelch circuitPLL Frequency SynthesizerThe PLL circuit generates the first local oscillator signal forreception and the RF signal for transmission. PLLThe frequency step of the PLL circuit is 5 or 6.25kHz. A16.8MHz reference oscillator signal is divided at IC401 by afixed counter to produce the 5 or 6.25kHz reference fre-quency. The voltage controlled oscillator (VCO) output signalis buffer amplified by Q410, then divided in IC401 by a dual-module programmable counter. The divided signal is com-pared in phase with the 5 or 6.25kHz reference signal in thephase comparator in IC401. The output signal from thephase comparator is filtered through a low-pass filter andpassed to the VCO to control the oscillator frequency. (SeeFig. 6.) VCOThe operating frequency is generated by Q406 in transmitmode and Q405 in receive mode. The oscillator frequency iscontrolled by applying the VCO control voltage, obtainedfrom the phase comparator, to the varactor diodes (D405 andD406 in transmit mode and D403 and D404 in receive mode).The TX/RX pin is set high in receive mode causing Q408 andQ407 to turn Q406 off, and turn Q405 on. The TX/RX pin isset low in transmit mode. The outputs from Q405 and Q406are amplified by Q410 and sent to the RF amplifiers. (See Fig.6.)D405,406Q406TX VCOQ410BUFFAMPD403,404Q405RX VCOQ407,408T/R SWChargepumpLPFPhasecomparator1/M1/N5kHz/6.25kHz5kHz/6.25kHzREFOSC16.8MHzPLLDATAIC401 : PLL ICQ404AMPRF amplifiersQ402,403TX/RX (CPU)Fig. 6 PLL circuitCIRCUIT DESCRIPTIONTM-271A/271E4 Unlock CircuitDuring reception, the 8RC signal goes high, the 8TC signalgoes low, and Q34 turns on. Q33 turns on and a voltage isapplied to 8R. During transmission, the 8RC signal goes low,the 8TC signal goes high and Q36 turns on. Q35 turns on anda voltage is applied to 8T.The CPU monitors the PLL (IC401) LD signal directly.When the PLL is unlocked during transmission, the PLL LDsignal goes low. The CPU detects this signal and makes the8TC signal low. When the 8TC signal goes low, no voltage isapplied to 8T, and no signal is transmitted. (See Fig. 7.)IC101CPUQ34SWQ33SWIC401PLLQ36SWQ35SWLD8RC8C8R 8T8TCPLL lock: LD “H”Fig. 7 Unlock circuitTransmitter System OutlineThe transmitter circuit produces and amplifies the desiredfrequency directly. It FM-modulates the carrier signal bymeans of a varicap diode. Power Amplifier CircuitThe transmit output signal from the VCO passes throughthe transmission/reception selection diode (D409) and ampli-fied by Q501, Q502 and Q503. The amplified signal goes tothe final amplifier (Q504) through a low-pass filter. The low-pass filter removes unwanted high-frequency harmonic com-ponents, and the resulting signal is transmitted through theantenna terminal. (See Fig. 8.) APC CircuitThe automatic transmission power control (APC) circuitdetects part of a final amplifier output with a diode (D606,D607) and applies a voltage to IC501. IC501 compares theAPC control voltage (PC) generated by the D/A converter(IC161) and DC amplifier (IC203) with the detection outputvoltage. IC501 generates the voltage to control Q503 andQ504 and stabilizes transmission output.The APC circuit is configured to protect over current ofQ503 and Q504 due to fluctuations of the load at the antennaend and to stabilize transmission output at voltage and tem-perature variations. (See Fig. 9.)RFAMPQ501DRIVEAMPQ503FINALAMPQ504PREDRIVEAMPQ502DCAMPIC203ANTSWD602,D603D605LPFANTPOWERDETD606D607IC501VR601APCCONTROLD409IC161(PC/TVO)(PC)Q411RF AMPQ501RF AMPQ502PREDRIVE AMPQ503ANTDRIVEAMPQ504FINALAMPIC4021/2DIVIDERIC161 Q406D/A CONVERTERD/A CONVERTERD/A CONVERTERX401TCXO16.8MHzVCOIC401PLLQ410BUFFERQ404RF AMPIC203BUFFERIC101IC161MIC KEYINPUTCPUIC161IC203SUMAMPIC202IC201MICMIC/IDCSPLATTERFILTERFig. 9 APC circuitFig. 8 Transmitter systemCIRCUIT DESCRIPTIONTM-271A/271E5Control CircuitThe CPU carries out the following tasks (See Fig. 10.):1) Controls the WIDE, NARROW, TX/RX outputs.2) Adjusts the AF signal level of the AF filter (IC251) andturns the filter select compounder on or off.3) Controls the display unit.4) Controls the PLL (IC401).5) Controls the D/A converter (IC161) and adjusts the vol-ume, modulation and transmission power. Memory CircuitThe transceiver has an 64k-bit EEPROM (IC66). TheEEPROM contains adjustment data. The CPU (IC101) con-trols the EEPROM through three serial data lines. (See Fig.11.)IC161D/AconverterIC401PLLIC101CPULDDTCKPLLEEEPCKIC101CPUIC66EEPROMEEPSDTEEPWP Display CircuitThe CPU (IC101) controls the display LCD and LEDs.When power is on, the LCD driver will use the BL line to con-trol the LCD illumination and key backlight LEDs.The brightness function is controlled by the switch Q12.The LCD driver (IC3) and CPU (IC101) communicate throughthe CE, CL, DI, DO lines. (See Fig. 12.) Key Matrix CircuitThe TM-271 front panel has function keys. Each of themis connected to a cross point of a matrix of the KI1 to KI3 andKSI to KS2 ports of the LCD driver.The LCD driver monitors the status of the KI1 to KI3 andKS1 to KS2 ports. If the state of one of the ports changes,the LCD driver assumes that the key at the matrix point corre-sponding to that port has been pressed. EncodeThe DCS and CTCSS signals are output from QT/DQT ofthe CPU (IC101) and summed with the external pin DI line bythe summing amplifier (IC203) and the resulting signal goesto the D/A converter (IC161). The DTMF signal is output fromDTMF pin of the CPU and summed with a MIC signal by thesumming amplifier (IC203), and the resulting signal goes tothe D/A converter (IC161).The D/A converter (IC161) adjusts the MOD level and thebalance between the MOD and CTCSS/DCS levels. Part of aCTCSS/DCS signal is summed with MOD and the resultingsignal goes to the VCOMOD pin of the VCO. This signal isapplied to a varicap diode in the VCO for direct FM modula-tion.IC3LCDdriverKI1KI2KI3KS2KS1FUNCREVCALLVFOMRMHz(Encoder)X401TCXOIC161D/AVCOIC203SUMAMPIC203SUMAMPIC401PLLTCXOMODVCOMODAmpDIQT/DQT(CPU1)DTMO(EVOL15)IC101CPUTONEDTMFFig. 10 Control circuitFig. 11 Memory circuitQ10SWQ6SWIC101CPUD2D4Q9SWD19D30Q12SWIC3LCDdriverCECLDIDOBLCOM0COM3SEG0SEG30LCDBRIFig. 12 Display circuitFig. 13 Key matrix circuitFig. 14 EncoderCIRCUIT DESCRIPTIONTM-271A/271E6 Decode CTCSS/DCSThe signal (W/NO (EVOL2) goes to DTMF IN (pin 95) ofCPU (IC101). The CTCSS/DCS signal will pass through thelow-pass filters in the CPU (IC101) and be decoded within theCPU (IC101). The DTMF signal will be decoded within theCPU (IC101). D/A ConverterThe D/A converter (IC161) is used to adjust MO modula-tion, AF volume, TV voltage, FC reference voltage, and PCPOWER CONTROL voltage level.Adjustment values are sent from the CPU as serial data.The D/A converter has a resolution of 256 and the followingrelationship is valid:D/A output = (Vin VDAref) / 256 x n + VDArefVin: Analog inputVDAref: D/A reference voltagen: Serial data value from the microprocessor (CPU)Power Supply CircuitWhen the power switch on the display unit is pressed, thepower port on the display unit which is connected port 17(POWER), goes low, then port 82 (SBC) goes high, Q32 turnson, SB SW (Q31) turns on and power (SB) is supplied to theradio.When the DC power supplied to the radio, the voltageregulator IC (IC33) supply into the CPU VDD and reset voltagedetect IC (IC34). IC34 will generate signal (RESET) in to thereset terminal on the CPU (IC101) to carry out a power ONreset. If DC power is less than about 9.5V, the radio is unableto power on.When the DC power voltage deceases from normal volt-age, the INT voltage detector IC (IC35) will set to high on CPUport 18 (INT) if B line will became less than about 9.5V. ThenCPU send to EEPROM (IC66) the backup data and go intoSTOP mode.This circuit has an overvoltage protection circuit. If a DCvoltage of 18V or higher is applied to the base of Q61, thisvoltage turns Q61 on and will set to high on CPU port 18(INT). Then CPU send to EEPROM (IC66) the backup dataand go into stop mode. (See Fig. 16.)IC101CPUDTMF IN W/NO (EVOL2)95Q71SWQ31SWQ32SWQ61SWIC33AVRD61D62BIC34RSTSBCIGNR77R76R39R40INT5MBATTIC101CPUPOWERSWPOWERRESET5MIC35INTSBIGNFig. 15 DecodeFig. 16 Power supply circuitCIRCUIT DESCRIPTIONData Terminal and Peripheral CircuitsCN2 (data terminal) is the data communications terminalon the TX/RX PCB. It handles transmission control, data in-put/output, and squelch signals.There are two data communications modes : 9600bpsmode and 1200bps mode. Unlike with 1200bps AFSK, withthis type of high-speed modulation, frequency modulation iscarried out after the digital base band signals (rectangularwave) are passed through a band limiting filter. For 9600bpsGMSK for example, compared to 4800Hz signals (nearly sinewave signals passed through a filter), these signals have ahissing sound like digital modulation when listened to by ear.Different types of modulation, such as GMSK is distin-guished by the type of band limiting filter.Pin Pin SpecificationNo. Name1 PKD bps switching 1200bps 9600bpsModulation input 400mVp-p 4Vp-pFrequency shift 3±0.5kHz 2.2±0.5kHz4 PR9 Output level 500mVp-p/10kAlways output during reception5 PR1 Output