Onkyo-CR305X-rec-sm维修电路原理图.pdf

CD RECEIVER MODEL CR-305X Ref.NO.3654 082000 TABLE OF CONTENTS CR-305X Specifications - Caution on replacement of optical pickup - Protection of eyes from laser bam during servicing - Service procedures - Front panel view - Rear panel view - Remote controller - Microprocessor connection diagram - Microprocessor terminal descriptions - IC Block diagram and descriptions - CD Mechanism exploded view - Replacement of optical pickup - Chassis exploded view parts list - Chassis exploded view - Block diagram - Wiring view - Printed circuit board view parts list -7 Schematic diagram (Amplifier section) - Printed circuit board view 1- Schematic diagram (CD resets at Low. (no pull-up resistance) 24C. OUTOTrack number count signal output. 25SENS1OOutputs FZC, DFCT1, TZC, BALH, TGH, FOH, ATSC, and others according to the command from CPU. 26SENS2OOutputs DFCT2, MIRR, BALL, TGL, FOL, and others according to the command from the CPU. 27FOKOFocus OK comparator output. 28 CC2IInput for the defect bottom hold output with capa- citance coupled. 29CC1ODefect bottom hold output. Connected internally to the interruption comparator input. 30CBIConnection pin for defect bottom hold capacitor. 31CPI 32RF_II 33RF_OO 34RF_MI Connection pin for MIRR hold capacitor. MIRR comparator non-inverted input. Input for the RF summing amplifier output with capa- citance coupled. RF sunning amplifier output. Eyepattern check point. RF summing amplifier inverted input. The RF amplifier gain is determined by the resistance connected between this pin and RFO pin. 35RFTCIExternal time constant setting pin during RF level control. 36LDOAPC amplifier output. 37PDIAPC amplifier input. 38PD1I 39PD2I RF I-V amplifier inverted input. Connect these pins to the photo diode A + C and B + D pins. 40FE_BIASIBias adjustment of focus error amplifier. Leave this pin open for automatic adjustment. 41FI 42IE 43EII-V amplifier E gain adjustment. (When not using automatic balance adjustment) 44VEE Negative power supply. 45TEOOTracking error amplifier output. E-F signal is output. 46LPFIIComparator input for balance adjustment. (Input from TEO through LPF) 47TEI ITracking error input. 48ATSC I Window comparator input for ATSC detection. 49TZC I Tracking zero-cross comparator input. 50TDFCTICapacitor connection pin for defect time constant. 51VCO(VCC + VEE)/2 direct voltage output. 52FZCIFocus zero-cross comparator input. CR-305X ? 12 ? CR-305X Q301:CXD2589Q (CD Digital Signal Processor) Bloch Diagram EFM demodurator Clock Generator OSC Error Corrector D/A Interface Serial-In Interface Over Sampling Digital Filter Timing Logic 3rd-Order Noise Shaper PWM PWM 16K RAM Digital OUT Digital CLV CPU Interface Servo Auto Sequencer Asymmetry Corrector Digital PLL Sub Code Processor C4M RF ASYI ASYO BIAS XPCK FILO FILI PCO CLTV FOK SEIN CNIN DATO XLTO CLKO SENS DATA XLAT CLOK XLON SCOR SBSO EXCK SQSO SQCK MDP DOUT LOUT2 AIN2 AOUT2 LOUT1 AIN1 AOUT1 XTSL VPCO VCKI V16M VCTL XUGF GFS EMPH WFCK C2PO LRCK PCMD BCK EMPHI LRCKI PCMDI BCKI SYSM RMUT LMUT XTAI XTAO PWMI XRST TES1 TEST SPOA SPOB 4039 38 37 36 35 31 33 4142434447 48 515049 52 53 545556 57 58 59 70 66 6567 62 71 767574 79 2 3 98 7654 10 11 12 13 1415 1617 18 21 23 24 28272625 29 30 22 51 25 2627 2847 49 54 5650 39 414355 40 42 44 62 24 23 79 2 3 70 71 52 35 37 38 36 48 30 31 29 33 18 10 11 12 13 146789 15 16 17 57 58 59 542122537475 766766 65 ? 13 ? Terminal description Pin No. SymbolI/O Description Pin No. Symbol I/O Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 VSS LMUT RMUT SQCK SQSO SENS DATA XLAT CLOK SEIN CNIN DATO XLTO CLKO SPOA SPOB XLON FOK VDD VSS MDP PWMI TEST TES1 VPCO VCKI V16M VCTL PCO FILO FILI AVSS CLTV AVDD RF BIAS ASYI ASYO LRCK LRCKI PCMD PCMDI O O I O O I I I I I O O O I I O I O I I I O I O I O O I I I I I O O I O I GND Left-channel zero detection flag. Right-channel zero detection flag. SQSO readout clock input. Sub Q 80-bit serial output. SENS output to CPU. Serial data input from CPU. Latch input from CPU. Serial data is latched at the falling edge. Serial data transfer clock input from CPU. SENS input from SSP. Track jump count signal input. Serial data output to SSP. Serial data latch output to SSP. Latched at the falling edge. Serial data transfer clock output to SSP. Microcomputer extended interface (input A). Microcomputer extended interface (input B). Microcomputer extended interface (output). Focus OK input. Used for SENS output and the servo auto sequencer. Power supply (+5V). GND Spindle motor servo control. Spindle motor external control input. TEST pin; normally GND. TEST pin; normally GND. Charge pump output for the wide-band EFM PLL. VCO2 oscillation input for the wide-band EFM PLL. VCO2 oscillation output for the wide-band EFM PLL. VCO2 control voltage input for the wide-band EFM PLL. Master PLL charge pump output. Master PLL (slave = digital PLL) filter output. Master PLL filter input. Analog GND. Master VCO control voltage input. Analog power supply (+5V). EFM signal input. Constant current input of the asymmetry circuit. Asymmetry comparator voltage input. EFM full-swing output (low = VSS, high = VDD). D/A interface. LR clock output f = Fs. LR clock input. D/A interface. Serial data output (twos complement, MSB first). D/A interface. Serial data input (twos complement, MSB first). D/A interface. Bit clock output. D/A interface. Bit clock input. GND Power supply (+5V). XUGF output. Switched to MNT1 or RFCK output by a command. XPLCK output. Switched to MNT0 output by a com- mand. GFS output. Switched to MNT3 or XRAOF output by a command. C2PO output. Switched to GTOP output by a com- mand. Crystal selector input. Low: 16.9344MHz; high: 33.8688MHz. 4.2336MHz output. 1/4 frequency-divided VCKI out- put in CAV-W mode. Digital Out output. Outputs a high signal when the playback disc has emphasis, and a low signal when there is no emphasis. Inputs a high signal when de-emphasis is on, and a low signal when de-emphasis is off. WFCK output. Outputs a high signal when either subcode sync S0 or S1 is detected. Sub P to W serial output. SBSO readout clock input. GND Power supply (+5V). Mute input. Active when high. Analog GND. Analog power supply (+5V). Left-channel analog output. Left-channel operational amplifier input. Left-channel LINE output. Analog GND. Power supply for master clock. Crystal oscillation circuit input. Input the external master clock via this pin. Crystal oscillation circuit output. GND for master clock. Analog GND. Right-channel LINE output. Right-channel operational amplifier input. Right-channel analog output. Analog power supply (+5V). Analog GND. System reset. Reset when low. Power supply (+5V). 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 O I O O O O I O O O I O O O I I O I O I O O I O I BCK BCKI VSS VDD XUGF XPCK GFS C2PO XTSL C4M DOUT EMPH EMPHI WFCK SCOR SBSO EXCK VSS VDD SYSM AVSS AVDD AOUT1 AIN1 LOUT1 AVSS XVDD XTAI XTAO XVSS AVSS LOUT2 AIN2 AOUT2 AVDD AVSS XRST VDD PCMD is an MSB first, twos complement output. GTOP is used to monitor the frame sync protection status. (High: sync protection window open.) XUGF is the frame sync obtained from the EFM signal, and a negative pulse. It is the signal before sync protection. XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge of XPLCK and the EFM signal transition point coincide. GFS goes high when the frame sync and the insertion protection timing match. RFCK is derived with the crystal accuracy. This signal has a cycle of 136s (during normal speed). C2PO represents the data error status. XRAOF is generated when the 16K RAM exceeds the 4F jitter margin. Notes) CR-305X ? 14 ? CR-305X Q401:TC9273N-007 (Analog function switch) Q402:TC9162AF Analog function switch 2 3 4 5 6 7 8 9 10 11 12 27 26 25 24 23 22 21 20 19 18 17 128 VSSVDD 13141516 GNDCK DATA STB LEVEL SHIFT AND SHIFT REGISTER S1 S2 S3 S4 S5 S6 S7 OUT S8 S9 OUT S1 S2 S3 S4 S5 S6 S7 OUT S8 S9 OUT 10BITS LATCH CIRCUIT 10BITS LATCH CIRCUIT 2 3 4 5 6 7 8 9 10 11 12 13 15 16 17 18 19 20 21 22 23 24 25 26 27 28141 VSSGND VDD S1 S2 S3 COM1 S4 S5 S6 COM2 S7 S8 COM3 ST S1 S3 S2 COM1 S4 S5 S6 COM2 S7 S8 COM3 CK DATA LEVEL SHIFTER LEVEL SHIFTER LATCH CIRCUIT LATCH CIRCUIT SHIFT REGISTER ? 15 ? 16 ? Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Level shift 4 BTLAMP 4 Level shift 1 BTLAMP 1 BTLAMP 3 BTLAMP 2 Level shift 3 Level shift 2 RESET Regulator Pin No.Pin NameDescription (Function) 1VCCPower supply (shorted with pin 30) 2MuteON/OFF control for all BTLAMP outputs 3VIN1BTLAMP 1 input 4VG1BTLAMP 1 input (for gain control) 5VO1BTLAMP 1 output (non-inverting side) 6VO2BTLAMP 1 output (inverting side) 7GNDGND (minimum electric potential) 8GNDGND (minimum electric potential) 9GNDGND (minimum electric potential) 10VO3BTLAMP 2 output (inverting side) 11VO4BTLAMP 2 output (non-inverting side) 12VG2BTLAMP 2 input (for gain control) 13VIN2BTLAMP 2 input 14REG OUTConnection for collector of external transistor (PNP); 5 V supply output 15REG INConnection for base of external transistor (PNP) 16RESReset output 17CDReset output delay time setting (with capacitor) 18VIN3BTLAMP 3 input 19VG3BTLAMP 3 input (for gain control) 20VO5BTLAMP 3 output (non-inverting side) 21VO6BTLAMP 3 output (inverting side) 22GNDGND (minimum electric potential) 23GNDGND (minimum electric potential) 24GNDGND (minimum electric potential) 25VO7BTLAMP 4 output (inverting side) 26VO8BTLAMP 4 output (non-inverting side) 27VG4BTLAMP 4 input (for gain control) 28VIN4BTLAMP 4 input 29VREFReferencevoltage input for level shift circuit 30VCCPower supply (shorted with pin 1) Vcc Vref VIN4 VG4 Vo8 Vo7 GND GND GND Vo6 Vo5 VG3 VIN3 CD RES Vcc Mute VIN1 VG1 Vo1 Vo2 GND GND GND Vo3 Vo4 VG2 VI2 Reg OUT Reg IN Q102:LA6541D (4-channel ridge Driver for Compact Dizcs)Q180:BU1923 (RDS Decoder( + (4) (3) (5) (6) (12) (11) (16) (1) (2) (10)(9) Measurement circuit Differential decoder Bi-phase decoder PLL 1187.5 Hz PLL 57 kHz RDS/ARI Reference clock (13)(14) (7)(8) 120 k? 100 k? 100 k? Analog Power supply Digital power supply anti-aliasing filter 8ch Switched capacitor filter Comparator RCLK QUAL RDATA T2T1 XOX1 VSS2 VDD2 VSS1 VDD1 VREF MUX VSS3CMP Pin name Demodulator quality Demodulator data Reference voltage Input Analog power supply GND Comparator input Test input Digital power supply Crystal oscillor - Demodulator clock Function Good data : High , bad data : Low Refer to output data trimming 1/2 VDD1 Composite signal input 4.5 V to 5.5 V - C-junction Open or connected to ground 4.5 V to 5.5 V Connects to 4.332 MHz oscillator - 1187.5 Hz clock Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol QUAL RDATA Vref MUX VDD1 Vss1 Vss3 CMP T2 T1 VDD2 Vss2 XI XO (NC) RCLK CR-305X ? 18 ? CR-305X ? 17? Q103:TA7291S (motor driver) Q691:TC7WU04FU (triple inverters) 1A 3Y 2A GND 1 2 3 45 6 7 8Vcc 1Y 3A 2Y Truth table AY L H H L INPUTOUTPUT IN1 0 1 0 1 IN2 0 0 1 1 OUT1 ? H L L OUT2 ? L H L MODE STOP CW/CCW CCW/SW BRAKE CCW : Counter clockwise diection CW : Clockwise diection Vcc REG PROTECTOR IN1IN2GND OUT1 OUT2 Vss Vref ? ? ? ? 28 159 3 6 7 S TSTEREO MUTING MIN kHz MHz MONOAUTOTRACKTIMER W.DAY W.END REC SLEEP C D MEMORY REPEAT RANDOM RDSPMAM S.BASS DIRECT a b c d e f g hj k m n p r 10G 9G 8G 7G 6G 5G 4G 3G 2G 1G Q751 : 10BT-167GK (FL TUBE) 10G9G8G7G6G5G4G3G2G1G P1-aaaaaaaa- P2W.DAYjjjjjjjjMUTING P3W.ENDhhhhhhhhMIN P4MEMORYkkkkkkkkS.BASS P5-bbbbbbbb- P6-ffffffff- P7-gggggggg- P8RECmmmmmmmmMHz P9-cccccccc- P10-eeeeeeee- P11REPEATnnnnnnnnkHz P12RANDOMrrrrrrrrrDIRECT P13-pppppppp- P14-dddddddd- P15TIMERTRACKAUTOMONOAMPMRDSS P16CD-Col-TSTEREO P17SLEEP-Dp- (9G - 2G) CR-305X ?1 9 ? 20 ? CD MECHANISM EXPLODEE VIEW(1)CD MECHANISM EXPLODEE VIEW(2) pickup drive unit 62 63 51 54 61 55 53 56 57 58 64 52 59 60 6 5 13 20 19 12 14 15 2 1 3 4 29 22 16 17 16 28 27 26 21 16 12 14 15 18 25 24 23 13 14 15 14 15 16 7 9 8 10 6 11 6 6 Ref. No.Part No.Description 12646-290-01Tray 2Stopper 32625-544-01Gear cover 42625-535-01Tray Gear 52625-546-01Chucking plate 6PTPWH2.6*7,Screw 72625-537-01Chucking yoke 81452-493-21Magnet 92625-541-02Damper 102646-291-01Chucking pulley 112646-288-01Sub chassis 122627-236-01Coil spring (front) 132627-235-01Coil spring (back) 142646-289-01Washer 15P2.6*10,Screw Ref. No.Part No.Description 162627-234-01Insulator 17KSM-213CCM 182625-552-06Main chassis 193319-501-51PTPWH2.6*16, Screw 202625-547-01Drive Gear 212625-545-04Control cam 221692-667-11Leaf switch 231564-721-11Socket 241640-523-11Loading motor assy 25X2625-117-1Loading motor 262625-274-02Middle gear 272625-536-02Loading pulley 283653-387-00LM belt 29B2.6*2.5, Screw Ref. No.Part No.Description 51X2625-984-1Motor chassis assy 52X2625-769-1Motor gear assy 532656-908-01Sled shaft 542625-188-02Gear A 557621-255-15P2x3, Screw 561572-085-11Leaf switch 571639-678-12Motor PC board 581564-722-11Socket 592627-003-02Gear B 602625-191-01Coil spring 612625-477-01Center ring 622641-386-01Special screw, 2*5 632625-625-01Reinforcement board 648848-483-05KSS-213C, Pickup The mechanical parts with no part number in the exploded views are not supplied. CR-305X ? 22 ? CR-305X ? 21 ? REPLACEMENT OF OPIAL PICKUPCHASSIS EXPLODED VIEW PARTS LIST The laser diode in the optical pickup block is so sensitive to static electricity,surge current and etc. That the components are liable to be broken down or its reliability remarkably deteriorated. During repair,carefully take the following precautions. Do not touch the optical pickup object lens with the hands. (5) Solder the LD short terminal 1 on mechanism (Fig-6) (6) Disconnect the flexible flat cable P352. (Fig-6) (7) Replace the optical pickup. (8) Connect the flexible flat cable P352. (Fig-6) (9) Unsolder the LD terminal 1 on mechanism. (Fig-6) (Fig-1) screw screw NAETC-6883 (Soldering side) LD short terminal 2 (Fig-6) LD short terminal 1 P352 to NAETC-6883 NAETC-6883 (Component side) (Fig-4) J293 NAETC-6883 (Fig-5) P351 to main PC board (NAAR-6875)