Goodmans-GDVX580-cd-sm维修电路原理图.pdf

Service Manual - GDVX580 GDVX580 Service Manual - GDVX580 RadioFans.CN 收音机爱 好者资料库 2 CONTENTS : 1.INFORMATIONS.3 Vibratto-II DVD Processor (ESS 66x8) 2. OPERATING INSTRUCTIONS.14 3. PRODUCT SPECIFICATIONS.24 4. TROUBLESHOOTING.25 5. MAINTENANCE INSTRUCTIONS.26 6. ELECTRICAL PART LIST.35 7. DISASSEMBLY AND REASSEMBLY.43 8. CIRCUIT DIAGRAMS.44 9. WIRING DIAGRAM.49 RadioFans.CN 收音机爱 好者资料库 3 1. INFORMATIONS Vibratto-II DVD Processor (ESS 66x8) Vibratto-II DVD Processor FEATURES: ? Single-chip DVD processoe incorporating all front-end and back-end functions ? Unified memory architecture ? Proven focusing, sledding, tracking, and CLV/CAV spindke servo control ? Proven ESS, EFM,?EFM+ demodulation, and EDC circuit ? Built-in ADCs and DACs for servo control signals ? Direct interface to ES6603 servo AFE chip ? Integrated NTSC/PAL encode with pixel-adaptive de-interlacer and five 10-bit 54MHz video DACs ? DVD-video, DVD-VR, VCD1.1 and 2.0, and SVCD ? DivX and MPEG-4 Advanced Simple profile at full screen(D1) ? Full DVD-audio support including MLP and LPCM decode, CPPM decryption, and watermark detection ? Media playback with CD-ROM, CD-R/RW, DVD-R/RW, and DVD+R/RW ? Up to 7.1 channel audio outputs ? Direct interface of 16 bit DRAM up to 128Mb capacity ? Direct interface for up to 4 banks of 8-bit EPROM or FLASH EPROM for up to 4MB per bank ? Macrovision 7.1 for NTSC/PAL (480p/576p) progressie scan video ? Simultaneous composite,S-video and YUV output ? CCIR656/601 yuv 4:2:2 output ? OSD controller supports 256 colors in 8 degrees of transparency ? Subpicture Unit(SPU) decoder supports karaoke iyric,subtitles,and EIA-608 compliant Line 21 Captioning. ? SmartBrght for clear and bright movie presentation. ? SmartColor for vivid flesh-tone image display. ? SmartLogo for custom JPEG wallpaper. ? JPEG digital photo CD support (Kodak Picture CD and Fujifilm FujiColor CD. ? ESS Music Slideshor. ? Bass management. ? Dolby Digital(AC-3),Dolby ProLogic,and ProLogicll. ? DTSsurround(ES6698D only). ? S/PDIF digital audio input and output. ? MPEG AAC and Multichannel. ? SRS TruSurround ? Professional karaoke with full scoring scheme. RadioFans.CN 收音机爱 好者资料库 4 Functional Description: The internal block digram for ESS 6698 RadioFans.CN 收音机爱 好者资料库 5 Pinout Diagram RadioFans.CN 收音机爱 好者资料库 6 ES6698 PIN DEXCRIPTION Names Pin Numbers I/P Definitions VD33 1.10.19.35.44.53.6 2.79.96.126.185. P I/O power supply. VID_XI 2 I Crystal input. VID_XO 3 O Crystal output. VID_XO 3 O Crystal output. CLK 4 I System clock. DMA11:0 5:8 11:17 20 O DRAM address bus. VX33 9.18.34.43.52.61.7 8. 95.119.127.186.20 8 G Ground for I/O power supply. DCAS# 21 O DRAM column address strobe (active-low). DCS1:0# 22.23 O DRAM chip select (active-low). DRAS2:0# 24.25.28 O DRAM row address strobe (active-low). VSS 26.70.86.137.197 G Ground for core power supply. VDD 27.71.87.138.198 P Core power supply. DSCK_EN O DRAM clock enable output . DOE# 29 O DRAM output enable(active-low). DWE# 30 O DRAM write enable(active-low). DB15:0 31:33,36:42,45:50 I/O DRAM data bus. DSCK 51 O Output clock to DRAM. DQM 54 O Data input/output mask. LA21:0 55:60,63:69,72:77 80:82 O RISC port address bus . LCS3:0# 83:85 88 O RISC port chip select (active-low). LWRLL# 89 O RISC port low-byte write enable(active-low). LOE# 90 O RISC port output enable (active-low). LD7:0 91:94,97:100 I/O RISC port data bus; (5V tolerant input). RSD 101 I Audio receive serial data; (5V tolerant input ). RBCK 102 I Audio receive bit clock; (5V tolerant input ). RWS 103 I Audio receive frame sync; (5V tolerant input ). VD33_PL 104 P Power for PLL blocks. VS33_PL 105 G Ground for PLL blocks. VREF I Internal voltage reference to video DAC. YUV1 106 O YUV pixel 1 output data . COMP I Compensation input . YUV3 107 O YUV pixel 3 output data . RSET I DAC current adjustment resistor input . YUV4 108 O YUV pixel 4 output data. FDAC 109 O Video DAC output. Refer to description and matrix for UDAC pin 115. RadioFans.CN 收音机爱 好者资料库 7 YUV7 O YUV pixel 7 output data . VDAC O Video DAC output . Refer to description and matrix for UDAC pin 115. YUV6 110 O YUV pixel 6 output data. Names Pin Numbers I/P Definitions VD33_DA 111 P Power for I/O power supply for VDAC. VS33-DA 112 G Ground for I/O power supply for VDAC. YDAC O Video DAC output. Refer to description and matrix for UDAC pin 115. YUV5 113 O YUV pixel 5 output data. CDAC O Video DAC output. Refer to description and matrix for UDAC pin 115. YUV2 114 O YUV pixel 2 output data . UDAC O Video DAC output. Pin 109 110 113 114 115 Valu e FDAC VDACYDAC CDACUDAC 0 CVBS/Chrom a CVBS 1 Y C N/A 1 CVBS/Chrom a CVBS 1 Y C CVBS2 2 CVBS/Chrom a N/A Y C N/A 3 CVBS/Chrom a CVBS 1 N/A N/A CVBS2 4 CVBS/Chrom a CVBS 1 N/A N/A N/A 5 CVBS/Chrom a CVBS 1 Y Pb Pr 6 CVBS/Chrom a N/A Y Pb Pr 7 N/A SYNCG B R 8 CVBS/Chrom a Chrom a Y Pb Pr 9 CVBS CVBS 1 G B R 10 CVBS CVBS 1 G R B 11 N/A SYNCG R B 12 CVBS/Chrom a N/A Y Pr Pb 13 CVBS/Chrom a CVBS 1 Y Pr Pb 14 Chroma Y G R B F: VCBS/chroma signal for simultaneous mode. Y: Luma component for YUV and Y/C processing. RadioFans.CN 收音机爱 好者资料库 8 C: Chrominance signal for Y/C processing. U: Chrominance component signal for YUV mode. V: Chrominance component signal for YUV mode. TWS 116 O Audio transmit frame sync output. RadioFans.CN 收音机爱 好者资料库 9 Names Pin Numbers I/P Definitions SEL_PLL2 I System and DSCK output clock frequency selection is made at the rising edge of RESET#. The matrix below lists the available clock frequencies and their respective PLL bit settings. Strapped to VCC or ground via 4.7-K resistor; read only during reset. SEL_PLL 2 SEL_PLL1SEL_PLL0 Clock Type(MHz) 0 0 0 CLK*4.5 0 0 1 CLK*5.0 0 1 0 Bypass 0 1 1 CLK*4.0 1 0 0 CLK*4.25 1 0 1 CLK*4.75 1 1 0 CLK*5.5 1 1 1 CLK*6.0 TSD0 O Audio transmit serial data port 0. SEL_PLL0 117 I Refer to the description and matrix for SEL_Pll2 pin 116. TSD1 O Audio transmit serial data port 1. SEL_PLL1 118 I Refer to the description and matrix for SEL_PLL2 pin 116. TSD2:3 120.121 O Audio transmit serial data ports 2 and 3. MCLK 122 I/O Audio master clock for audio DAC. TBCK 123 O Audio transmit bit clock. SPD_DOBM O S/PDIF output . SEL_PLL3 124 I Clock source select. Strapped to VCC or ground via 4.7K read only during reset . SEL_PLL3 Clock Source 0 Crystal oscillator 1 CLK input SPDIF_IN 125 I S/PDIF input; (5V tolerant input). WBLCLK 128 O DVD-RAM wobble detector circuit clock source to preamp. WBL 129 O DVD-RAM wobble output. LG 130 O DVD-RAM land/groove flag. IP2 131 I DVD-RAM header position index 2. IP1 132 I DVD-RAM header position index 1. FLAG3:0 133:136 O To monitor servo status . TEXI 139 I High-speed tracking error input . TESTAD 140 I Test AD input . SBAD 141 I Sub-beam addition input signal . FEI 142 I Focus input error signal. AVSS_AD 143 G Analog ground for ADC block . RadioFans.CN 收音机爱 好者资料库 10 CEI 144 I Center error input signal . TEI 145 I Tracking error input signal . RFRP 146 I RF ripple/envelope input signal. AVDD3_AD 147 P Analog power supply for ADC block. VREF21 148 O 2.1V reference voltage. VREF09 149 O 0.9Vreference voltage. VREF15 150 O 1.5V reference voltage. Names Pin Numbers I/P Definitions IREF 151 I Servo data PLL interface reference current generator connect a resistor between this pin and ground to set reference current . AVDD3_DS 152 P Analog power supply for data slicer .block. IPIN 153 I Inverting input of data slicer . RFIN 154 I Analog RF signal input after passing through equalizer(minus) RFIP 155 I Analog RF signal input after passing through equalizer(plus). DSSLV 156 O Data slicer level output. AVSS_DS 157 G Analog ground for data slicer block. AVSS_PL 158 G Analog ground for data PLL block. PDOFTR1 159 O Servo data PLL phase detector filter pin number 1. FDO 160 O Servo data PLL output node of frequency detector charge pump. FTROPI 161 I Servo data PLL input node of loop filter OP circuit . AVDD3_OL 162 P Analog power supply for data PLL block . PLLFTR1 163 I Servo data PLL loop filter pin number1. PLLFTR2 164 I Servo data PLL loop filter pin number2. VREF0 165 O Servo data PLL reference voltage output. AWRC 166 I/O Auto wide range control VCO signal from/to AWRC DAC. AVSS_DA 167 G Analog ground for DAC part. RFRPCTR 168 I/O Central level of RFRP. TRAY 169 O Output voltage level for tray buffer IC. AVDD3_DA 170 P Analog power supply for DAC part . SPINDLE 171 O Output voltage level for spindle buffer IC. FOCUS 172 O Output voltage level for focus buffer IC. SLEGP 173 O Output voltage level for Sledge buffer IC(plus). SLEGN 174 O Output voltage level for Sledge buffer IC(minus). TRACK 175 O Output voltage level for tracking buffer IC. TESTDA 176 O Test DA output . FGIN 177 I Spindle hall sensor input . PHOI 178 I Sledge photo interrupt signal input. SCSJ 179 O Chip selection signal to RF chip (serial data enable). SDATA 180 I/O Data signal from/to RF chip. SCLK 181 O Serial clock source to RF chip. DFCT 182 I Defect flag input signal. RadioFans.CN 收音机爱 好者资料库 11 LDC 183 O Laser diode on/off control output. SPDON 184 O Spindle power driver on/off control output. GPIO9:4 187:192 I/O General-purpose input/output used for servo control; (5V tolerant input.) EAUX3:0 193:196 I/O Extended auxiliary ports;(5V tolerant input). ICDATA I/O IC data I/O;(5V tolerant input). AUX0 199 I/O Auxiliary port (open collector);(5V tolerant input). IC_CLK I/O IC clock I/O;(5V tolerant input). AUX1 200 I/O Auxiliary port (open collector);(5V tolerant input). IOW# O I/O Write strobe(LCS1)(active-low). HSYNC# I/O Horizontal sync (active low);(5V tolerant input). AUX2 201 I/O Auxiliary port ;(5V tolerant input). Names Pin Numbers I/P Definitions IOR# O I/O Read strobe (LCS1)(active low). VSYNC# I/O Vertical sync (active-low);(5V tolerant input ). AUX3 202 I/O Auxiliary port;(5V tolerant input). C2PO I Error correction flag from CD;(5V tolerant input). AUX4 203 I/O Auxiliary port;(5V tolerant input). AUX5:6 204:205 I/O Auxiliary ports ;(5V tolerant input). IR I Infrared remote control input;(5V tolerant input). AUX7 206 I/O Auxiliary port;(5V tolerant input ). RESET# 207 I Reset input (active low );(5V tolerant input). 101 I Audio receive serial data inputRSD;(5V tolerant input). 102 I Audio receive bit clock input RBCK:(5V tolerant input ). 103 I Audio receive frame sync inputRWS;(5V tolerant input). 116 O Audio transmit frame sync outputTWS. 117.118.120.121 O Audio transmit serial data outputs TSD3:0. 122 I/O Audio DAC master clockMCLK. 123 O Audio transmit bit clock outputTBCK. 124 O Sony/Philips Digital Interface audio output SPD_DOBM. Audio Port Interface 125 I Sony/Philips Digital Interface audio Input SPDIF_IN;(5V tolerant input). 193:196 I/O Extended auxiliary ports EAUX3:0;(5V tolerant input). 199.200 I/O Open collectors AUX1:0,(5V tolerant input). Auxiliary Port Interface 201:206 I/O Primary auxiliary port I/Os AUX7:2;(5V tolerant input). 2 I 27-MHz crystal clock input VID_XI. 3 O 27-MHz crystal clock outputVID_XO. 4 I System clock CLK. 29 O DRAM clock enable output DSCK_EN. 51 O Output clock DSCK to video memory (DRAM). 116:118 I Clock frequency select PLL outputs SEL_PLL2:0. Clock Inetface and Reset 207 I Reset input (active-low)RESET#;(5V tolerant input). 106:110.113:115 O Pixel data outputs YUV7:0. Display Interface 201 I/O Horizontal syncHSYNC#;(%V tolerant input). RadioFans.CN 收音机爱 好者资料库 12 202 I/O Vertical sync VSYNC#;(5V tolerant input ). 55:60.63:69.72:77. 80:82 O RISC port address bus LA21:0to EPROM or Flash memory. 83:85 O RISC port chip select outputs LCS2:0#to EPROM or Flash memory. 89 O RISC port low-byte write enable outputLWRLL#to EPROM or Flash memory. 90 O RISC port output enableLOE#to EPROM and Flash memory. EPROM/Flas h ROM and RISC Port Intetface 91:94.97:100 I/O RISC port data bus LD7:0to EPROM or Flash memory (5V tolerant input ). 106 I Video DAC reference voltage inputVREF. Filter and Reference voltang Interface 107 I Compensation inputCOMP. Front Panel Display Interface 206 I Infrared remote control input IR;(5V tolerant input). Names Pin Numbers I/P Definitions General-Purp ose 187:192 I/O General purpose I/OGPIO9:4;(5V tolerant input). 199 I/O IC data I/O12C_DATA;(5V tolerant input). IC Bus Interface 200 I/O IC clock I/O12C_CLK;(5V tolerant input). 1.10.19.35.44.53.6 2.79.96.126.185 P I/O power supply VD33. 9.18.34.43.52.61.7 8.95.119.127.186. 208 G I/O ground VS33. 26.70.86.137.197 G Ground for core power VSS. 27.71.87.138.198 P Core power supply VDD. 104 P Power supply for PLL block .VD33_PL. 105 G Ground for PLL block VS33_PL. 111 P Power supply for video DACVD33_DA. 112 G Ground for video DACVS33_DA. 143 G Analog ground for ADCAVSS_AD. 147 P Analog power supply for ADCAVDD3_AD. 152 P Analog power supply for data slicer AVDD3_DS. 157 G Analog ground for data slicerAVSS_DS. 158 G Analog ground for data PLL AVSS_PL. 162 P Analog power supply for data PLLAVDD3_PL. 167 G Analog ground for DACAVSS_DA. Power and Ground 170 P Analog power supply for DACAVDD3_DA. Serial Port Interface 203 I C2PO error correction flag from CDC2PO;(5V tolerant input). RadioFans.CN 收音机爱 好者资料库 13 153 I Inverting input of data slicer IPIN. 154 I Analog RF signal input after passing through equalizer(minus) RFIN. 155 I Analog RF signal input after passing through equalizer(plus) RFIP. Servo Data Slicer Interface 156 O Data slicer level outputDSSLV. RadioFans.CN 收音机爱 好者资料库 14 2.OPERATING INSTRUCTIONS 1. GENERAL SETUP Pressing the SETUP button on remote control during STOP or PLAY mode to SETUP MENU. . sing Cursor to select GENERAL SETUP. Press ENTER to enter GENERAL SETUP page. a.TV DISPLAY Using cursor to move to desired setting and press ENTER to confirm. NORMAL/PS 4 x 3 Pan Scan Full screen of picture on TV. Normally, left and right edges cannot be shown. NORMAL/LB 4 x 3 Letter Box Orginal ratio of aspect. WIDE 16 : 9 Widescreen b. PIC MODE (PICTURE MODE) ( FOR PROGRESSIVE-SCAN MODEL ) SETUP MENU - MAIN PAGE GENERAL SETUP SPEAKER SETUP AUDIO SETUP PREFERENCE EXIT SETUP TV DISPLAY PIC MODE ANGLE MARK OSD LANG CAPTIONS SCR SAVER MAIN PAGE - GENERAL PAGE - TV DISPLAYNORMAL P/S PIC MODENORMAL L/B ANGLE MARKWIDE OSD LANG CAPTIONS SCR SAVER MAIN PAGE - GENERAL PAGE - TV DISPLAY PIC MODEAUTO ANGLE MARKFILM OSD LANGVIDEO CAPTIONSSMART SCR SAVERSUPER SMART MAIN PAGE - GENERAL PAGE - TV DISPLAY PIC MODEAUTO ANGLE MARKHI-RES OSD LANGNON-FLICKER CAPTIONS SCR SAVER MAIN PAGE - GENERAL PAGE - RadioFans.CN 收音机爱 好者资料库 15 c.ANGLE MARK This feature is functioned only for the disc, which has ANGLE function: When the ANGLE MARK is set ON, the screen displays the mark. When the ANGLE MARK is set OFF, the mark is not displayed. d. OSD LANG (ON SCREEN DISPLAY LAN