Denon-AVR3801-avr-sm维修电路原理图.pdf

Hi-Fi Component SERVICE MANUAL MODEL AVR-3801 AV SURROUND RECEIVER ? Some illustrations using in this service manual are slightly different from the actual set. RadioFans.CN 收音机爱 好者资料库 2 AVR-3801 SPECIFICATIONS ! ! ! ! ! AUDIO SECTION Power Amplifier Rated output:Front:105W + 105W (8/ohms, 20Hz 20kHz with 0.05% T.H.D.) 150W + 150W (6/ohms, 1kHz with 0.7% T.H.D.) 180W + 180W (6/ohms, EIAJ) Center:105W (8/ohms, 20Hz 20kHz with 0.05% T.H.D.) 150W (6/ohms, 1kHz with 0.7% T.H.D.) 180W + 180W (6/ohms, EIAJ) Surround:105W + 105W (8/ohms, 20Hz 20kHz with 0.05% T.H.D.) 150W + 150W (6/ohms, 1kHz with 0.7% T.H.D.) 180W + 180W (6/ohms, EIAJ) Surround Back: 105W + 105W (8/ohms, 20 Hz 20kHz with 0.05% T.H.D.) 150W + 150W (6/ohms, 1kHz with 0.7% T.H.D.) 180W + 180W (6/ohms, EIAJ) Dynamic power:140W 2ch (8/ohms) 210W 2ch (4/ohms) 240W 2ch (2/ohms) Output terminals:Front, Center, Surr. Back/Multi Zone: 6 16/ohms Surround:A or B 6 16/ohms A + B 8 16/ohms Analog Input sensitivity/input impedance:200mV/47k/kohms Frequency response:10Hz 100kHz: +0, 3dB (DIRECT model) S/N:102dB (DIRECT mode) Distortion:0.005% (20Hz 20kHz) (DIRECT mode) Rated output:1.2V Digital D/A output:Rated output 2V (at 0dB playback) Total harmonic distortion 0.008% (1 kHz, at 0 dB) S/N ratio 102dB Dynamic range 96dB Digital input:Format Digital audio interface Phono equalizer (PHONO input REC OUT) Input sensitivity:2.5mV RIAA deviation:1dB (20Hz to 20kHz) Signal-to-noise ratio:74dB (A weighting, with 5mV input) Rated output/Maximum output:150mV/8V Distortion factor:0.03% (1kHz, 3V) ! ! ! ! ! VIDEO SECTION Standard video jacks Input/output level and impedance:1Vp-p, 75/ohms Frequency response:5Hz 10MHz +0, 3dB S-video jacks Input/output level and impedance:Y (brightness) signal 1Vp-p, 75/ohms C (color) signal 0.286Vp-p, 75/ohms Frequency response:5Hz 10MHz +0, 3dB Color component video jacks Input/output level and impedance:Y (brightness) signal 1Vp-p, 75/ohms CB (blue) signal 0.7Vp-p, 75/ohms CR (red) signal 0.7Vp-p, 75/ohms Frequency response:5Hz 27MHz +0, 3dB ! ! ! ! ! TUNER SECTION FM (note: V at 75/ohms, 0dBf=1 10-15 W)AM Receiving Range:87.50MHz 107.90MHz520kHz 1710kHz (for North America and multiple voltage models)(for North America and Multiple voltage models) 87.50MHz 108.00MHz522kHz 1611kHz (for Europe, China, Hong Kong, Taiwan R.O.C. and Multiple voltage models)(for Europe, China, Hong Kong, Taiwan R.O.C. and multiple voltage models) Usable Sensitivity:1.0V (11.2dBf)18V 50dB Quieting Sensitivity:MONO: 1.6V (15.3dBf) STEREO: 23V (38.5dBf) S/N (IHF-A):MONO: 80dB STEREO: 75dB Total Harmonic Distortion (at 1kHz):MONO: 0.15% STEREO: 0.3% ! ! ! ! ! GENERAL Power supply:AC120V, 60Hz (for North America and Taiwan R.O.C. models) AC230V, 50Hz (for Europe model) AC220V, 50Hz (for China model) AC115V/230V, 50/60Hz (for Hong Kong and Multiple voltage models) Power consumption:7.0A (for North America model) 400W (for Europe, China, Hong Kong and Multiple voltage models) 360W (for Taiwan R.O.C. model) 2.0W Max (Standby) Maximum external dimensions:434 (W) 171 (H) 416 (D)mm (17-3/32 6-11/32 16-3/8) Weight:17.0kg (37 lbs 8 oz) ! ! ! ! ! REMOTE CONTROL UNIT(RC-883: for North America, China, Hong Kong, Taiwan R.O.C. and Multiple voltage models) (RC-884: for Europe model) Batteries:R6P/AA Type (three batteries) External dimensions:61 (W) 230 (H) 34 (D)mm (2-13/32 9-1/16 1-11/32) Weight:200g (Approx. 7 oz) (including batteries) * For purposes of improvement, specifications and design are subject to change without notice. SAFETY PRECAUTIONS The following check should be performed for the continued protection of the customer and service technician. LEAKAGE CURRENT CHECK Before returning the unit to the customer, make sure you make either (1) a leakage current check or (2) a line to chassis resistance check. If the leakage current exceeds 0.5 milliamps, or if the resistance from chassis to either side of the power cord is less than 460 kohms, the unit is defective. Spec.p6500/09/12, 14:36Page 2Adobe PageMaker 6.5J/Win RadioFans.CN 收音机爱 好者资料库 3 AVR-3801 WIRE ARRANGEMENT If wire bundles are untied or moved to perform adjustment or parts replacement etc.,be sure to rearrange them neatly as they were originally bundled or placed afterward. Otherwise, incorrect arrangement can be a cause of noise generation. Wire arrangement viewed from the top 4 AVR-3801 DISASSEMBLY (Follow the procedure below in reverse order when reassembling) 1. Top Cover Remove 3 screws 1 on the rear and 6 screws 2 on both sides to detach the Top Cover as shown in the arrow direction. 2. Front Panel (1) Remove 7 screws 3 from the top and bottom edges of the Front Panel. (2) Release 4 top and bottom hooks, then detach the Front Panel as shown in the arrow direction. Top Cover 3. Inner Panel Pull out the Inner Panel in the arrow direction after removing 3 screws 4. Inner Panel Hook 2 2 1 3 3 3 Hook Hook Hook Front Panel 4 4 Disassembly.p6500/09/12, 14:31Page 4Adobe PageMaker 6.5J/Win 5 AVR-3801 4. Inner Panel Assy (1) Remove 3 round and 1 square knobs, and unscrew 4 nuts. (2)Remove 15 screws 5 fixing each P.W.B. Round Knob 5 5 5 Nut Square Knob Round Knob Nut 5. Power Transformer (1) Remove 4 screws fixing the Power Transformer and 4 connectors. (2) Be careful when removing the Power Transformer as it is heavy. Before proceeding to the next stop, take off the Power Transformer. Disassembly.p6500/09/12, 14:31Page 5Adobe PageMaker 6.5J/Win 6 AVR-3801 7. Regulator Unit Take off the Regulator Unit ? ? as shown in the arrow direction after removing 8 screws ? ?. ? ? ? ? 6. Component Video Unit / PRE-OUT Unit / AMP Connect Unit (1) Remove 9 screws 6 to detach Component Video Unit 7 and Pre-out Unit 8. (2) Take off the Amp Connect Unit 9 as shown in the arrow direction after removing 1 screw ? ?. 8 6 7 9 ? ? Disassembly.p6500/09/12, 14:32Page 6Adobe PageMaker 6.5J/Win 7 AVR-3801 8. S-Video / C-video / Audio-in Edge detection is “Ed”; Detection by both shifting is “E Serial data detection is “S” (Serial data output is also “S”). Res: State at reset. “H”= Outputs High Level at reset “L”= Outputs Low Level at reset “Z”= Becomes High impedance mode at reset Ini: Initial output state. Function: Function and logical level explanation of signals to be interface. 124 25 40 4164 65 80 13 AVR-3801 1_TMP88CU74F.p6500/09/12, 15:15Page 12-13Adobe PageMaker 6.5J/Win TMP93CS41F (AU: IC301) NameFunction TMP93CS41F Terminal Function Pin No. 1V REFLA/D ref. GND 2A VssA/D GND 3A VccAD +5V 4_NMIINot used (fixed to H) 5P70/TI0_DEMOD RESETOCEdLLDemodulator reset output (L: Reset) 6P71/TO1DEMOD ONOCEdLLDemodulator osc. control output (H: Osc.) 7P72/TO2FAN1OCEdLLFAN control output (H: ON, L: OFF) 8P73/TO3FAN2OCEdLLFAN control output (H: Hi, L: Low 4 ? ? ? ? ? ? ? ) 6 ? 6 6 ? ? ? ? ? 3 : & ? BA15218 UPC4570GE BA4510F LM833MX (EX: IC810) (AU: IC112) (EX: IC301, 308, 701) (AU: IC109, 731734) (AU: IC603) (EX: IC801804) (CO: IC103) A OUTPUT A INPUT A+INPUT V B OUTPUT V B INPUT B +INPUT 1 2 3 45 7 8 6 NJM2229S (AC: IC305) 324 6 7 8 910 1112 13 14 1 15 16 5 1 16 Sync Sepa Sync Det Phase Det Vsync Sepa 32fH VCO 1/32 PQ15RW11 (RE: IC907) 4 3 2 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? W29EE011P-90 (AU: IC303) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 5 ? ? ? A0 - A16 DQ0 - DQ7 CE OE WE VDD GND NC ? ? ? ? ? ? ? ? Terminal Function NameFunction Address input Data in/output Chip enable Output enable Write enable Power terminal GND No connection SN74HC151NS (AU: IC510) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 5 D2 D1 D0 Y W S D4 D5 D6 D7 A B C 3 2 1 0 Y W Strobe GND Vcc 4 5 6 7 A B C Data Inputs Data Select Data Inputs Outputs 74VHC123A (AU: IC517) 15 1 2 3 4 5 6 7 8 5 16 14 13 12 11 10 9 CLR QQ QQCLR 1A 1B 1CLR 1Q 2Q 2Cex1 2Rext/Cext GND Vcc 1Rex/Cext 1Cext 1Q 2Q 2CLR 2B 2A 74LVX157 (AU: IC525) 1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Vcc ST 4A 4B 4Y 3A 3B 3Y SELECT 5 SEL SN74LV4040APW (AU: IC606) ? ( < ( % ? ? ? / ? ? ? ? ? ? ? ? ? ? ? ? ? 1 2 3 4 5 6 7 8 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 9 ? ? ? ? ? ? . ? + ? ? ? ? ? ? ? ( < ( % ? ( < ( % ? ? ? ? ? ? ? / ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? . ? + ? ? ? ? ? ? Truth Table 22 AVR-3801 LH28F800BVE-BTL90 (AU: IC403) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE Vss DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE Vss CE A0 A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE RESET Vpp WP RDY/BSY A18 A17 A7 A6 A5 A4 A3 A2 A1 Terminal Function SymbolFunction Name A0A18 DQ0DQ14 DQ15A-1 CE OE BYTE WE RDY/BSY RESET NC VDD, Vpp Vss Address input Data in/output Data in/output/Address input Chip enable input Output enable input Word/bute select input Write enable input Ready/busy output Hardware reset input No connection Power GND WPWrite protect input AD1854 (AU: IC701, 702, 703, 704) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DGND MCLK CLATCH CCLK CDATA 384/256 X2MCLK ZEROR DEEMP 96/48 AGND OUTR+ OUTR ? FILTR DVDD SDATA BCLK L/RCLK PD/RST MUTE ZEROL IDPM0 IDPM1 FILTB AVDD OUTL+ OUTL ? AGND NameFunction Terminal Function No. 1DGNDIDigital Ground. 2MCLKIMaster Clock Input 3CLATCHILatch input for control data 4CCLKIControl clock input for control data 5CDATAISerial control input 6384/256ISelects the master clock mode 7X2MCLKISelects internal clock doubler (LO) or internal clock=MCLK (HI) 8ZERORORight Channel Zero Flag Output 9DEEMPIDe-Emphasis 1096/48ISelects 48kHz (LO) or 96kHz Sample Frequency Control 11,15 AGNDIAnalog Ground 12OUTR+ORight Channel Positive line level analog output 13OUTR-ORight Channel Negative line level analog output 14FILTROVoltage Reference Filter Capacitor Connection 16OUTL-OLeft Channel Negative line level analog output 17OUTL+OLeft Channel Positive line level analog output 18AVDDIAnalog Power supply 19FILTBOFilter Capacitor connection 20IDPM1IInput serial data port mode control one 21IDPM0IInput serial data port mode control zero 22ZEROLOLeft Channel Zero Flag output 23MUTEIMute. Assert HI to mute both stereo analog output 24PD/RSTIPower-Down/Reset 25L/R CLKILeft/Right clock input for input data 26BCLKIBit clock input for input data 27SDATAISerial input 28DVDDIDigital Power Supply I/O 23 AVR-3801 HY57V16160D (AU: IC417, 418) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 DQ15 DQ14 VssQ DQ12 VDDQ DQ11 DQ10 VssQ DQ9 DQ8 VDDQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 Vss DQ0 DQ1 VssQ DQ2 DQ3 VDDQ DQ4 DQ5 VssQ DQ6 DQ7 VDDQ LDQM WE CAS RAS CS A11 A10 A0 A1 A2 A3 VDD25 49 50VDD DQ13 Vss SN74AHCT573PW (AU: IC411) SN74LV573ANS (AU: IC302, 412) 1 2 3 4 5 6 7 8 10 9 20 19 18 17 16 15 14 13 12 11 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SN74LV00APW (AU: IC408, 529) ? ? ? ? ? ) ? ? ? ? ? ) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ) ? ? ? ? ? ) ? ? ? 74VHC02MTC (AU: IC410) ? ) ? ? ? ? ? ) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ) ? ? ? ? ? ) ? ? ? ? SN74AHCT08PW (AU: IC421, 422) ? ? ? ? ? ) ? ? ? ? ? ) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ) ? ? ? ? ? ) ? ? ? SN74LV14APW (AU: IC530, 532) ? ? ? ? ) ? ? ? ) ? ? ? ) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ) ? ? ? ) ? ? ? ) MM74HCU04SJ (RE: IC704) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ) ? ? ? ) ? ? ? ) ? ? ? ? ? ? ? ) ? ? ? ) ? ? ? ) Terminal Function PinPin NameDescription CLKClock The system clock input. All other inputs are referenced to the SDRAM on the rising edge of CLK. CKEClock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh CSChip SelectCommand input enable or mask except CLK, CKE and DQM BABank AddressSelect either one of banks during both RAS and CAS activity A0A10Address Row Address: RA0RA10, Column Address: CA0CA7, Auto-Pre charge flag: A10 RAS, CAS, WE Row Address Strobe, Column Address Strobe, Write Enable RAS, CAS and WE define the operation. Refer function truth table for details LDQM, UDQM Data Input/Output Mask DQM control output buffer in read mode and mask input data in write mode DQ0DQ15Data Input/OutputMultiplexed data input/output pin VDD/VssPower Supply/GroundPower supply for internal circuit and input buffer VDDQ/VssQ Data Output Power/Ground Power supply for DQ NCNo ConnectionNo connection 24 AVR-3801 MM74HC4052N (AC: IC371, 375) (RE: IC401) 1 2 VEE 3 4 5 6 7 89 ? ? 11 ? ? ? ? ? ? ? ? 12 Y0 Y2 Y1 INH Vss VDD X2 X1 X0 A B Y-COM Y3X-COM X3 LEVEL CONVER -TER BINARY TO 1 of 4 DECODER WITH INHIBIT 13 X 3 Y Y3 4 Y2 2 Y1 5 Y0 1 X3 11 X2 15 X1 14 X0 12 VEE 7 B 9 INH 6 VSS 8 A 10 VDD16 MM74HC4053N (RE: IC403) C9 1 2 VEE 3 4 5 6 7 89 ? ? 11 ? ? ? ? ? ? ? ? 12 Y1 Y0 Z-COM Z0 INH Vss VDD Y-COM X-COM X1 X0 C A B Z1 LEVEL CONVER -TER BINARY TO 1 of 2 DECODER WITH INHIBIT 14 X Z1 3 Z0 5 Y1 1 Y0 2 X1 13 X0 12 VEE7 B10 INH6 Vss8 A11 VDD16 15 Y 4 Z L-LD2 9 L-ch7 to 91decoder R-ch latch circuit R-ch7 to 91decoder 10 19 NC 22 NC 3 2 4 5 6 7 8 11 12 13 14 28 27 26 25 24 23 21 20 18 17 16 15 1 NC L-OUT NC L-IN L-LD1 L-A-GND NC CS1 NC GND CK VSSVDD NC R-OUT R-LD1 R-LD2 R-A-GND NC CS2 NC STB DATA R-IN 50k/ 91STEP VR Same as L-ch L-ch latch circuit Shift register (24Bit) Level shift circuit 1 28 14 TC9459N (EX: IC805809) SN74HC153NS (RE: IC705, 706) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1G B 1C3 1C2 1C1 1C0 1Y GND Vcc 2G A 2C3 2C2 2C1 2C0 2Y ? ? 1C31C21C11C01Y ? ? ? ? ? ? 2C32C22C12C02Y ? ? ? ? Europe model only SAA6579T (CO: IC301) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 QUAL RDDA VREF MUX VSS A CIN SCOUT RDCL T57 OSCO OSCI VDD D TEST MODE VDD A VSS D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 QUAL RDDA VREF MUX VDD A VSS A CIN SCOUT MODE TEST VSS D VDD D OSCI OSCO T57 RDCL Quality indication output. RDS data output. Multiplex signal input. +5V power supply for analog part. Ground for analog part (0V). Subcarrier input to comparator. Subcarrier ouput of reconstruction filter. Oscillation mode/test control input. Test enable input. Ground for digital part (0V). +5V power supply for digital part. Oscillator input. Oscillator output. 57kHz clock signal output. RDS clock output. Pin No. SymbolFunction SAA6579T Terminal Function Europe model only LC7074M (CO: IC302) OSC1 GND GND RES CLOCK-IN DATA-IN CORR. SEL CL. ED. SEL +5V 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 OSC2 GND CLOCK-OUT DATA-OUT DATA START ERROR CORRECTION