Denon-AVR2313-avr-sm维修电路原理图.pdf

D Note 1) Parameter Symbol Min Max Units Power Supplies Analog Digital |AVSS-DVSS| (Note 2) AVDD DVDD GND -0.3 -0.3 - 6.0 6.0 0.3 V V V Input Current (any pins except for supplies) IIN - 10mA Digital Input Voltage VIND -0.3 DVDD+0.3 V Ambient Operating Temperature Ta -40 85 C Storage Temperature Tstg -65 150 C Note 1. 電圧対値。 Note 2. AVSSDVSS接続下。 注意: 値超条件使用場合、破壊。 通常動作保証。 推奨動作条件 (AVSS, DVSS=0V; Note 1) Parameter Symbol Min Typ Max Units Power Supplies (Note 3) Analog Digital AVDD DVDD 4.75 4.75 5.0 5.0 5.25 5.25 V V Voltage Reference VREF AVDD-0.5- AVDD V Note 3. AVDDDVDD立上考必要。 注意: 本記載条件以外使用関、当社責任負十分 注意下。 185 H27U1G8F2BTR-BC (HDMI : U2603) H27U1G8F2BTR-BC Pin Function Rev 1.1 / Sep. 20095 1 H27U1G8F2B Series 1 Gbit (128 M x 8 bit) NAND Flash VCC VSS WP CLE ALE RE WE CEIO0IO7 R/B NC NC NC NCNC NCNC NC CLE ALEVss Vss Vss Vcc Vcc NC NC NC WP RE CE WERB NC NC NC NC NC NC NC NC NC NC NC NC NC I/O0 I/O1 I/O9 I/O2 I/O3 I/O10 I/O11I/O4 I/O15 I/O12I/O14 I/O13 I/O6 I/O7 I/O5 NC NCNCNC NC PRE I/O8 NC NCNC NCNC A B C D E F G H J K L M 1 2 3 4 5 6 7 8 9 10 ? ? ? Figure 2 : 48-TSOP1 / 63-FBGA Contact, x8 Device IO7 - IO0Data Input / Outputs CLECommand latch enable ALEAddress latch enable CEChip Enable RERead Enable WEWrite Enable WPWrite Protect R/BReady / Busy VccPower Supply VssGround NCNo Connection Figure 1 : Logic Diagram Table 1 : Signal Names ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Rev 1.1 / Sep. 20096 1 H27U1G8F2B Series 1 Gbit (128 M x 8 bit) NAND Flash 1.2 PIN DESCRIPTION Table 2 : Pin Description NOTE : 1. A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations. Pin NameDescription IO0 IO7 DATA INPUTS/OUTPUTS The IO pins allow to input command, address and data and to output data during read / program operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to High-Z when the device is deselected or the outputs are disabled. CLE COMMAND LATCH ENABLE This input activates the latching of the IO inputs inside the Command Register on the Rising edge of Write Enable (WE). ALE ADDRESS LATCH ENABLE This input activates the latching of the IO inputs inside the Address Register on the Rising edge of Write Enable (WE). CE CHIP ENABLE This input controls the selection of the device. WE WRITE ENABLE This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise edge of WE. RE READ ENABLE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. WP WRITE PROTECT The WP pin, when Low, provides an Hardware protection against undesired modify (program / erase) operations. R/B READY BUSY The Ready/Busy output is an Open Drain pin that signals the state of the memory. Vcc SUPPLY VOLTAGE The Vcc supplies the power for all the operations (Read, Write, Erase). VssGROUND NCNO CONNECTION 186 H27U1G8F2BTR-BC Block Diagram Rev 1.1 / Sep. 200915 1 H27U1G8F2B Series 1 Gbit (128 M x 8 bit) NAND Flash Figure 4 : Block Diagram ADDRESS REGISTER/ COUNTER PROGRAM ERASE CONTROLLER HV GENERATION COMMAND INTERFACE LOGIC COMMAND REGISTER DATA REGISTER IO RE BUFFERS Y DECODER PAGE BUFFER X D E C O D E R 1024 Mbit + 32 Mbit NAND Flash MEMORY ARRAY WP CE WE CLE ALE A27 A0 187 A3V56S30FTP-G6 (HDMI:U2604,2605) A3V56S30FTP A3V56S40FTP 256M Single Data Rate Synchronous DRAM Revision 1.1 Mar., 2010Page 2 / 39 CLK : Master Clock DQM : Output Disable / Write Mask (A3V56S30FTP) CKE : Clock Enable DQMU,L : Output Disable / Write Mask (A3V56S40FTP) /CS : Chip Select A0-12 : Address Input /RAS : Row Address Strobe BA0,1 : Bank Address /CAS : Column Address Strobe Vdd : Power Supply /WE : Write Enable VddQ : Power Supply for Output DQ0-7 : Data I/O (A3V56S30FTP) Vss : Ground DQ0-15 : Data I/O (A3V56S40FTP) VssQ : Ground for Output BA0 BA1 Vdd DQ0 VddQ DQ1 DQ2 VssQ DQ3 DQ4 VddQ DQ5 DQ6 VssQ DQ7 Vdd DQML /WE /CAS /RAS /CS A10(AP) A2 A3 Vdd A0 A1 Vdd DQ0 VddQ NC DQ1 VssQ NC DQ2 VddQ NC DQ3 VssQ NC Vdd NC /WE /CAS /RAS /CS BA0 BA1 A10(AP) A2 A3 Vdd A0 A1 DQM CKE Vss DQ15 VssQ DQ14 DQ13 VddQ DQ12 DQ11 VssQ DQ10 DQ9 VddQ DQ8 Vss NC DQMU CLK CKE A12 A11 A8 A7 A6 A5 A4 Vss A9 Vss DQ7 VssQ NC DQ6 VddQ NC DQ5 VssQ NC DQ4 VddQ NC Vss NC CLK A12 A11 A8 A7 A6 A5 A4 Vss A9 PIN CONFIGURATION (TOP VIEW) PIN CONFIGURATION (TOP VIEW) x8 x16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2332 2431 2530 2629 2728 Vdd DQ0 VddQ NC DQ1 VssQ NC DQ2 VddQ NC DQ3 VssQ NC Vdd NC /WE /CAS /RAS /CS BA0 BA1 A10(AP) A0 A1 A2 A3 Vdd Vss DQ7 VssQ NC DQ6 VddQ NC DQ5 VssQ NC DQ4 VddQ NC Vss NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 Vss 188 A3V56S30FTP-G6 Pin Function A3V56S30FTP A3V56S40FTP 256M Single Data Rate Synchronous DRAM Revision 1.1 Mar., 2010Page 4 / 39 Pin Descriptions SYMBOLTYPEDESCRIPTION CLKInput Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CKEInput Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank), or CLOCK SUSPEND operation (burst / access in progress). CKE is synchronous except after the device enters self refresh mode, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during self refresh mode, providing low standby power. CKE may be tied HIGH. /CSInput Chip Select: /CS enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when /CS is registered HIGH. /CS provides for external bank selection on systems with multiple banks. /CS is considered part of the command code. /CAS, /RAS, /WE Input Command Inputs: /CAS, /RAS, and /WE (along with /CS) define the command being entered. DQM, DQML, DQMU, Input Input / Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output disable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. DQM corresponds to DQ0DQ7 (A3V56S30FTP). DQML corresponds to DQ0DQ7, DQMU corresponds to DQ8DQ15 (A3V56S40FTP). BA0, BA1Input Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. A0A12Input A0-12 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-12. The Column Address is specified by A0-9(x8) and A0-8(x16). A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. DQ0DQ15I/O Data Input / Output: Data bus. NC Internally Not Connected: These could be left unconnected, but it is recommended they be connected or VSS. VddQSupply Data Output Power: Provide isolated power to output buffers for improved noise immunity. VssQSupply Data Output Ground: Provide isolated ground to output buffers for improved noise immunity. VddSupply Power for the input buffers and core logic. VssSupply Ground for the input buffers and core logic. 189 A3V56S30FTP-G6 Block Diagram LAN8720A (HDMI:U2802) A3V56S30FTP A3V56S40FTP 256M Single Data Rate Synchronous DRAM Revision 1.1 Mar., 2010Page 3 / 39 Note:This figure shows the A3V56S30FTP The A3V56S40FTP configuration is 8192x512x16 of cell array and DQ0-15 Type Designation Code A 3 56 F G6 Speed Grade 75： 133MHzCL=3 7： 143MHzCL=3 6： 166MHzCL=3 G： Green Package Type TP：TSOP (II) Process Generation Function Reserved for Future Use Organization 2n3：x8, 4：x16 SDR Synchronous DRAM Density 56：256M bits Interface V：LVTTL Memory Style (DRAM) Zentel DRAM Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet SMSC LAN8720A/LAN8720Ai9Revision 1.3 (04-20-11) DATASHEET Chapter 2 Pin Description and Configuration Note:When a lower case “n” is used at the beginning of the signal name, it indicates that the signal is active low. For example, nRST indicates that the reset signal is active low. Note:The buffer type for each signal is indicated in the BUFFER TYPE column. A description of the buffer types is provided in Section 2.2. Figure 2.1 24-QFN Pin Assignments (TOP VIEW) VSS SMSC LAN8720A/LAN8720Ai 24 PIN QFN (TOP VIEW) MDIO 1 2 3 4 5 6 7 8 9 10 11 12 18 17 16 15 14 13 24 23 22 21 20 19 VDDCR XTAL1/CLKIN XTAL2 LED1/REGOFF LED2/nINTSEL VDD2ATXD1 TXD0 TXEN nRST nINT/REFCLKO MDC VDD1A TXN TXP RXN RXP RBIAS CRS_DV/MODE2 RXER/PHYAD0 VDDIO RXD0/MODE0 RXD1/MODE1 190 LAN8720A Pin Function LAN8720A Block Diagram Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet SMSC LAN8720A/LAN8720Ai15Revision 1.3 (04-20-11) DATASHEET 2.1 Pin Assignments Table 2.8 24-QFN Package Pin Assignments PIN NUMPIN NAMEPIN NUMPIN NAME 1VDD2A13MDC 2LED2/nINTSEL14nINT/REFCLKO 3LED1/REGOFF15nRST 4XTAL216TXEN 5XTAL1/CLKIN17TXD0 6VDDCR18TXD1 7RXD1/MODE119VDD1A 8RXD0/MODE020TXN 9VDDIO21TXP 10RXER/PHYAD022RXN 11CRS_DV/MODE223RXP 12MDIO24RBIAS Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Revision 1.3 (04-20-11)8SMSC LAN8720A/LAN8720Ai DATASHEET Figure 1.1 System Block Diagram Figure 1.2 Architectural Overview RMII Logic Interrupt Generator LEDs PLL Receiver DSP System: Clock Data Recovery Equalizer Squeltch SAA7121 PINNING SYMBOLPINI/ODESCRIPTION res.1reserved SP2Itest pin; connected to digital ground for normal operation AP3Itest pin; connected to digital ground for normal operation LLC4Iline-locked clock; this is the 27 MHz master clock for the encoder VSSD15Idigital ground 1 VDDD16Idigital supply voltage 1 RCV17I/Oraster control 1 for video port; this pin receives/provides a VS/FS/FSEQ signal RCV28I/Oraster control 2 for video port; this pin provides an HS pulse of programmable length or receives an HS pulse MP79I MPEG port; it is an input for“CCIR 656” style multiplexed Cb Y, Cr data MP610I MP511I MP412I MP313I MP214I MP115I MP016I VDDD217Idigital supply voltage 2 VSSD218Idigital ground 2 RTCI19IReal Time Control input; if the LLC clock is provided by an SAA7111 or SAA7151B, RTCI should be connected to pin RTCO of the decoder to improve the signal quality res.20reserved SA21Ithe I2C-bus slave address select input pin; LOW: slave address = 88H, HIGH = 8CH res.22reserved res.23reserved C24Oanalog output of the chrominance signal VDDA125Ianalog supply voltage 1 for the C DAC res.26reserved Y27Oanalog output of VBS signal VDDA228Ianalog supply voltage 2 for the Y DAC res.29reserved CVBS30Oanalog output of the CVBS signal VDDA331Ianalog supply voltage 3 for the CVBS DAC VSSA132Ianalog ground 1 for the DACs VSSA233Ianalog ground 2 for the oscillator and reference voltage XTALO34Ocrystal oscillator output (to crystal) XTALI35Icrystal oscillator input (from crystal); if the oscillator is not used, this pin should be connected to ground VDDA436Ianalog supply voltage 4 for the oscillator and reference voltage XCLK37Oclock output of the crystal oscillator 193 R2A15218FP (INPUT : IC4210) 8-CHANNEL ELECTRONIC VOLUME With 14-Input selector And Tone control R2A15220FPR2A15220FP PRELIMINARY Notice ; This is not a final specification. Some parametric limits are subject to change. 2 / 18 CONFIDENTIAL R2A15220FP-87D BLOCK DIAGRAM AND PIN CONFIGURATION (TOP VIEW) AGND SWC SLC INLB/RECL2 INRB/RECR2 INR11/RECR5 INL10/RECL4 RECR3 INL11/RECL5 FLIN1 RECL3 CIN1 FRIN1 SLIN1 SWIN1 AVEE MUTE FLIN2 FRIN2 SLIN2 SRIN2 CIN2 SWIN2 SBLIN2 SBRIN2 AVCC TREL BASSL1 BASSL2 FLOUT FLC FROUT AGND FRC ADCR SBLIN1 SRIN1 SBRIN1 SBL OUT ADCL SBR OUT SLOUT SBRC SROUT SWOUT SRC COUTINL5 INL1 INR1 INL2 INR2 INL3 INR3 INL4 INR4 INR5 INL6 INR6 INL7 INR7 INL8 INR8 INLA/RECL1 INRA/RECR1 INL9 INR9 SUBR1 SUBL1 INR10/RECR4 DATA CLOCK BASSR1 BASSR2 AGND AGND SBRCIN SBLCIN AGND SBLC FR Pre-OUT FL Pre-OUT SBR Pre-OUT TRER SUBR2 SUBL2 SRCIN SLCIN SR Pre-OUT SL Pre-OUT SBL Pre-OUT INR12 INL12 INR13 INL13 INR14 INL14 CC AGND DGND REC ATT 0/-6/-12/-18dB Bass/ Treble -14+14dB (2dB step) +42-95dB, -(0.5dBstep) +42-95dB, -(0.5dBstep) +42-95dB, -(0.5dBstep) +42-95dB, -(0.5dBstep) +42-95dB, -(0.5dBstep) +42-95dB, -(0.5dBstep) Tone +420dB (0.5dBstep) Tone Bass/ Treble -14+14dB (2dB step) 0-95dB, - (0.5dBstep) +420dB (0.5dBstep) 0-95dB, - (0.5dBstep) MCU I/F AVEE AVCC Bypass Tone Tone+MIX Bypass Tone Tone+MIX MAIN SUB MAIN SUB 81828384858687888990919293949596979899100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 5049484746454443424140393837363534333231 MAIN SUB1 SUB2 194 R2A15218FP Pin Function 8-CHANNEL ELECTRONIC VOLUME With 14-Input selector And Tone control R2A15220FPR2A15220FP PRELIMINARY Notice ; This is not a final specification. Some parametric limits are subject to change. 3 / 18 CONFIDENTIAL R2A15220FP-87D PIN DESCRIPTION PIN No. Name Function 49DATA Input pin of control data 50CLOCKInput pin of control clock Output pin of FL/FR/C/SW/SL/SR/SBL/SBR channel FRIN2, FLIN2, SRN2,SLIN2, SWIN2,CIN2, SBRIN2,SBLIN2 43,42, 41,40, 39,38, 37,36 Multi Input pin of L/R/C/SW/SL/SR/SBL/SBR channel (Multi IN 1/2) Output pin for L/R channel REC Output Frequency characteristic setting pin of L/R channel tone control (Treble) 27,30 TREL, TRER 25,26, 28,29 22,20, 16,14, 10, 8, 2, 100 FROUT,FLOUT, COUT,SWOUT, SROUT, SLOUT, SBROUT,SBLOUT BASSL1,BASSL2 BASSR1,BASSR2 FLIN1, FRIN1, CIN1,SWIN1, SLIN1,SRIN1, SBLIN1,SBRIN1 90,91, 92,93, 94,95, 96,97 Frequency characteristic setting pin of L/R channel tone control (Bass) 24,18, 17,13, 12, 6, 4, 98 FRC,FLC, CC,SWC, SRC,SLC, SBRC,SBLC Connects capacitor for reducing click noise of L/R/C/SW/SL/SR/SBL/SBR channel volume INL1,INL2, INL3,INL4, INL5,INL6,INL7,INL8, INL9,INL12,INL13,INL14 Input pin of L/R channel (Input Selector) 57,59,61,63, 65,67,69,71, 75,83,85,87 INR1,INR2, INR3,INR4, INR5,INR6,INR7,INR8, INR9,INR12,INR13,INR14 56,58,60,62, 64,6668,70, 74,82,84,86 53,54ADCL, ADCROutput pin for L/R channel ADC 88,89 1,5,9,15, 21,55,98 AGND Analog ground of internal circuit 3