Denon-AVR983-avr-sm维修电路原理图.pdf

SERVICE MANUAL MODELAVR-2803/983 AVC-2870 AV SURROUND RECEIVER/AMPLIFIER For U.S.A., Canada, Europe, Asia, China, Hong Kong, Taiwan R.O.C., Korea Edge detection is “Ed”; Detection by both shifting is “E Serial data detection is “S” (Serial data output is also “S”). Res: State at reset. “H”= Outputs High Level at reset “L”= Outputs Low Level at reset “Z”= Becomes High impedance mode at reset STBY: State of port when STANDBY mode. “O/L” = Output port and “L” “I”= Input port Stop: State of port when Stop mode. “O/L”= Output port and “L” “I”= Input port 22 22AVR-2803/983/AVC-2870 BU4094BCF (CO: IC503) EXP1A(RECA)Video input switching (RECOUT SELECT) EXP2B(RECB)Video input switching (RECOUT SELECT) EXP3C(RECC)Video input switching (RECOUT SELECT) IC503 EXP4D(INA)Video output switching (INPUT SELECT) EXP5E(INB)Video output switching (INPUT SELECT) EXP6F(INC)Video output switching (INPUT SELECT) EXP7S1Video output switching EXP8S2Video output switching FunctionPortSymbol STROBE 1 2 3 4 5 6 7 89 10 11 16 15 14 13 12 DATA CLOCK Q1 Q2 Q3 Q4 VSS VDD OE Q5 Q6 Q7 Q8 QS QS BU4094BCF Terminal Function 23 23AVR-2803/983/AVC-2870 LC89057W (AD: IC520) LC89057W Terminal Function Function Pin No. Pin Name 1RXOUTOInput bi-phase select data output terminal 2RX0ITTL compatible digital data input terminal 3RX1ICoaxial compatible amp built-in digital data input terminal 4RX2ITTL compatible digital data input terminal 5RX3ITTL compatible digital data input terminal 6DGNDDigital GND 7DVDDDigital power 8RX4ITTL compatible digital data input terminal 9RX5/VIITTL compatible digital data/Validity flag input terminal for modulation 10RX6/UIITTL compatible digital data/User data input terminal for modulation 11DVDDDigital power for PLL 12DGNDDigital GND for PLL 13LPFOPLL loop filter connecting terminal 14AVDDAnalog power for PLL 15AGNDAnalog GND for PLL 16RMCKORMCK clock output terminal (256fs, 512fs, XIN, VCO) 17RBCKO/IRBCK clock in/output terminal (64fs) 18DGNDDigital GND 19DVDDDigital power 20RLRCKO/IRLRCK clock in/output terminal (fs) 21RDATAOSerial audio data output terminal 22SBCKOSBCK clock output terminal (32fs, 64fs, 128fs) 23SLRCKOSLRCK clock output terminal (fs/2, fs, 2fs) 24SDINISerial audio data input terminal 25DGNDDigital GND 26DVDDDigital power 27XMCKOOsc. amp output terminal I/O 36 RERR1RXOUT 35 INT2RX0 34 CKST3RX1 33 AUDIO/VO4RX2 32 EMPHA/UO5RX3 31 DGND6DGND 30 DVDD7DVDD 29 XIN8RX4 28 XOUT9RX5/VI 27 XMCK10RX6/UI 26 DVDD11DVDD 25 DGND12DGND 24SDIN37DO 23SLRCK38DI 22SBCK39CE 21RDATA40CL 20RLRCK41XMODE 19DVDD42DGND 18DGND43DVDD 17RBCK44TMCK/PIO0 16RMCK45TBCK/PIO1 15AGND46TLRCK/PIO2 14AVDD47TDATA/PIO3 13LPF48TXO/PIOEN TOP VIEW 1RXOUT 32 EMPHA/UO 33 AUDIO/VO 35 INT 40 CL 39 CE 38 DI 28 XOUT 29 XIN 27 XMCK 34 CKST 41 XMODE Input Selector 2RX0 3RX1 4RX2 5RX3 8RX4 9RX5/VI 10RX6/UI 37DO 36RERR 21RDATA 24SDIN 16RMCK 17RBCK 20RLRCK 22SBCK 23SLRCK 13LPF 44TMCK/PIO0 45TBCK/PIO1 46TLRCK/PIO2 47TDATA/PIO3 48TXO/PIOEN Clock Selector C bit, U bit PLL Demodulation & Lock Detect Microcontroller I/F Data Selector I/N Modulation or Parallel Port 24 24AVR-2803/983/AVC-2870 TC94A27UG(AD:IC371,376) Function Pin No. Pin NameI/O * For latch-up countermeasure, perform each power supply ON/OFF in the same timing. 28XOUTOXtal osc. connecting output terminal 29XINIXtal osc. connection, external clock input terminal (24.576MHz or 12.288MHz) 30DVDDDigital power 31DGNDDigital GND 32EMPHA/UOI/OEmphasis information/U-data output/Chip address setting terminal 33AUDIO/VOI/ONon-PCM detect/V-flag output/ Chip address setting terminal 34CKSTI/OClock switch transition period output/Demodulation master or slave function switching terminal 35INTI/OInterrupt output for com (Interrupt factor selectable)/Modulation or general I/O switching terminal 36RERROPLL lock error, data error flag output 37DOOcom I/F, read out data output terminal (3-state) 38DIIcom I/F, write data input terminal 39CEIcom I/F, chip enable input terminal 40CLIcom I/F, clock input terminal 41XMODEISystem reset input terminal 42DGNDDigital GND 43DVDDDigital power 44TMCK/PIO0I/O256fs system clock input for modulation/General I/O in/output terminal 45TBCK/PIO1I/O64fs bit clock input for modulation/General I/O in/output terminal 46TLRCK/PIO2I/Ofs clock input for modulation/General I/O in/output terminal 47TDATA/PIO3I/OSerial audio data input for modulation/General I/O in/output terminal 48TXO/PIOENO/IModulation data output/ General I/O enable input terminal NC L-TVR-REFB L-TVR-1NB L-MVR-1NB L-MVR-OUTB L-TVR-OUTB L-MVR-AGNDB2 L-MVR-AGNDARE L-MVR-AGNDARE L-MVR-AGNDA2 NC L-MVR-AGNDB1 NC 12 1110987654 321 13 14 15 16 17 19 18 20 21 22 44 43 42 41 40 39 37 38 36 35 34 23242526273029283132 33 R-TVR-REFB R-TVR-1NB R-MVR-1NB R-MVR-OUTB R-TVR-OUTB R-MVR-AGNDB2 R-MVR-AGNDA1 R-MVR-AGNDA2 R-MVR-OUTA NC R-MVR-AGNDB1 L-MVR-INA R-MVR-INA L-TVR-INA L-TVR-OUTA L-TVR-REPA R-TVR-REF R-TVR-INA R-TVR-OUTA NC CS1 VDD TEST GND MUTEM CS2 CK MUTE VSS STB DATA LatchLatch Level shift circuit Test & auto clear circuit Timing generating circuit Latch Latch LatchLatchLatch LatchLatchLatchLatch Decoder circuit 24 bit shift register Decoder circuit Latch 25 25AVR-2803/983/AVC-2870 AD1835 (AD: IC509) PIN FUNCTION DESCRIPTIONS Input/ Pin NumberMnemonicOutputDescription 1, 39DVDDDigital Power Supply. Connect to digital 5 V supply. 2CLATCHILatch Input for Control Data 3CINISerial Control Input 4PD/RSTIPower-Down/Reset 5, 10, 16, 24, 30, 35AGNDAnalog Ground 6, 12, 25, 31OUTLNxODACx Left Channel Negative Output 7, 13, 26, 32OUTLPxODACx Left Channel Positive Output 8, 14, 27, 33OUTRNxODACx Right Channel Negative Output 9, 15, 28, 34OUTRPxODACx Right Channel Positive Output 11, 19, 29AVDDAnalog Power Supply. Connect to analog 5 V supply. 17FILTDFilter Capacitor Connection. Recommended 10 F/100 nF. 18FILTRReference Filter Capacitor Connection. Recommended 10 F/100 nF. 20ADCLNIADC Left Channel Negative Input 21ADCLPIADC Left Channel Positive Input 22ADCRNIADC Right Channel Negative Input 23ADCRPIADC Right Channel Positive Input 36M/SIADC Master/Slave Select 37DLRCLKI/ODAC LR Clock 38DBCLKI/ODAC Bit Clock 40, 52DGNDDigital Ground 4144DSDATAxIDACx Input Data (Left and Right Channels) 45ABCLKI/OADC Bit Clock 46ALRCLKI/OADC LR Clock 47MCLKIMaster Clock Input 48ODVDDDigital Output Driver Power Supply 49ASDATAOADC Serial Data Output 50COUTOOutput for Control Data 51CCLKIControl Clock Input for Control Data 1 2 3 4 5 6 7 8 9 10 11 12 13 AGND AVDD OUTRP2 OUTRN2 OUTLP2 OUTLN2 OUTRP1 OUTRN1 OUTLP1 OUTLN1 PD/RST CIN CLATCH DVDD OUTLN3 OUTLP3 OUTRN3 OUTRP3 OUTLN4 OUTLP4 OUTRN4 OUTRP4 AGND DLRCLK DBCLK DGND 14151617181920212223242526 27 28 29 30 31 32 33 34 35 36 37 38 39 52515049 484746454443424140 FILTD FILTR AGND M/S AGND AVDD ADCLN ADCLP ADCRN ADCRP AGND AGND DGND CCLK COUT ASDATA ODVDD MCLK ALRCLK ABCLK DSDATA4 DSDATA3 DSDATA2 DSDATA1 DVDD AVDD AD1835 TOP VIEW (Not to Scale) NC ? NO CONNECT 26 26AVR-2803/983/AVC-2870 M35015-210SP(CV:IC453) 1 2 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 20 OSC1 OSC2 CS SCK SIN AC VDD2 CVIDEO LECHA CVIN VDD1 VERT* HOR* OSCIN OSCOUT P3 P2 P1 P0 Vss CS SCK SIN VDD120 AC Vss VDD2 P1 P0 CVIN LECHA CVIDEO OSCOUT OSCIN HOR*VERT*OSC2OSC1 INPUT CONTROL CIRCUIT INDICATION OSCILLATOR DATA CONTROL CIRCUIT ADDRESS CONTROL CIRCUIT TIMING GENERATOR INDICATION CONTROL REGISTER INDICATION RAM INDICATION CHARACTER ROM BLINKING CIRCUIT SHIFT REGISTER INDICATION CONTROL CIRCUIT READ OUT ADDRESS CONTROL CIRCUIT IINDICATION LOCATION DETECTION CIRCUIT H COUNTER SYNC SIGNAL SWITCHING CIRCUIT SYNC SIGNAL DIS- CRIMINATING CIRCUIT OSC CIRCUIT FOR SYNC SIGNAL GENERATION TIMING GENERATOR NTSC VIDEO OUTPUT CIRCUIT 6 11 5 4 3 7 121918 17 16 8 9 10 12 13 P214 P315 () M35015-210SP Terminal Function Pin No.SymbolNameI/OFunction 1OSC1Osc. circuit ext.IExternal terminal for indication oscillator circuit. Standard OSC. freq. is approx. 7MHz. 2OSC2terminal.OWith this OSC. freq., decides horizontal indication and character width. 3CSChip select inputI Chip select terminal and turns to “L” when transfer serial data. Hysteresis input. Pull up resistor is built-in. 4SCKSerial clock inputI Takes in serial data of SIN at SCK rise when CS terminal is in “L”. Hysteresis input. Pull up rersist is built-in. 5SINSerial data inputI Serial input of register for indication control and data, and address for indication data memory. Hysteresis input. Pull up rersistor is built-in. 6ACAuto-clear inputI Resets internal circuit of IC at “L” mode. Hysteresis input. Pull up resistor is built-in. 7VDD2Power supplyPower supply terminal of analog system. Connect to +5V. 8CVIDEO Combined video output O Output terminal of combined video signal. Outputs 2Vp-p combined signal. Character output, etc. Overlap CVIN signal and outputs at superimpose. 9LECHA Character level input I Input terminal deciding character output level in combined video signal. Color of character is white. 10CVIN Combined video input I Input terminal of external combined video signal. Character output etc. overlap this external combined video signal. 11VssGroundGround terminal. Connect to GND. 12P0Output port P0O General output or character background signal BL NK1* output is switchable. Polarity can be selected at ROM mask. 13P1Output port P1O General output or character background signal CO1* output is switchable. Polarity can be selected at ROM mask. 14P2Output port P2O General output or character background signal BLNK2* output is switchable. Polarity can be selected at ROM mask. 15P3Output port P3O General output or character background signal CO2* output is switchable. Polarity can be selected at ROM mask. 16OSCOUTOTerminal for external use of sync signal OSC. circuit. Use the freq.: 14.32MHz at NTSC 17OSCINIsystem, 17.73MHz at PAL system, 14.30MHz at MPAL system. 18HOR* Horizontal sync signal I Inputs horizontal sync signal. Hysteresis input. 19VERT* Vertical sync signal Input vertical sync signal. Hysteresis input. Polarity can be selected at ROM mask. 20VDD1Power supplyIPower supply terminal of digital system. Connect to +5V. Ext. terminal for sync sig. OSC. Circuit 27 27AVR-2803/983/AVC-2870 ADSST-MEL100(DS:IC801) Note : Note : When this IC is defecitive, replace P.W.B. Unit Assy NCA01 BMSTRA02 BMS_BA03 SPIDSA04 EBOOTA05 LBOOTA06 SCLK2A07 SD3BA08 L0DAT4A09 L0ACKA10 L0DAT2A11 L1DAT6A12 L1CLKA13 L1DAT2A14 NCA15 FLAG10E01 RESET_BE02 FLAG8E03 SD0AE04 VDDEXTE05 VDDINTE06 VDDEXTE07 VDDINTE08 VDDEXTE09 VDDINTE10 VDDEXTE11 L0DAT0E12 DATA39E13 DATA43E14 TRST_BB01 TD1B02 RPBAB03 MOSIB04 SFS0B05 SCLK1B06 SD2BB07 SD3AB08 L0DAT7B09 L0CLKB10 L0DAT1B11 L1DAT4B12 L1ACKB13 L1DAT0B14 NCB15 FLAG5F01 FLAG7F02 FLAG9F03 FLAG6F04 VDDINTF05 GNDF06 GNDF07 GNDF08 GNDF09 GNDF10 VDDINTF11 DATA37F12 DATA40F13 DATA38F14 TMSC01 EMU_BC02 GNDC03 SPICLKC04 SD08C05 SD1AC06 SD2AC07 SFS2C08 SFS3C09 L0DAT6C10 L1DAT7C11 L1DAT3C12 L1DAT1C13 DATA45C14 DATA47C15 FLAG1G01 FLAG2G02 FLAG4G03 FLAG3G04 VDDEXTG05 GNDG06 GNDG07 GNDG08 GNDG09 GNDG10 VDDEXTG11 DATA34G12 DATA35G13 DATA33G14 DATA41E15 IRQ2_BJ01 ID1J02 ID2J03 ID0J04 VDDEXTJ05 GNDJ06 GNDJ07 GNDJ08 GNDJ09 GNDJ10 VDDEXTJ11 DATA26J12 DATA24J13 DATA25J14 DATA27J15 ADDR14N01 ADDR15N02 ADDR10N03 ADDR5N04 ADDR1N05 MS0_BN06 BR5_BN07 BR2_BN08 BRSTN09 SDCKEN10 CS_BN11 CLK_CFG1 N12 CLK_CFG0 N13 AVDDN14 DMARI1_BN15 DATA36F15 TIMEXPK01 ADDR22K02 ADDR20K03 ADDR23K04 VDDINTK05 GNDK06 GNDK07 GNDK08 GNDK09 GNDK10 VDDINTK11 DATA22K12 DATA19K13 DATA21K14 DATA23K15 ADDR13P01 ADDR9P02 ADDR8P03 ADDR4P04 MS2_BP05 SBTS_BP06 BR4_BP07 BR1_BP08 SDCLK1P09 SDCLK0P10 REDYP11 CLKINP12 DQMP13 AVSSP14 DMAR2_BP15 DATA32G15 ADDR19L01 ADDR17L02 ADDR21L03 ADDR2L04 VDDEXTL05 VDDINTL06 VDDEXTL07 VDDINTL08 VDDEXTL09 VDDINTL10 VDDEXTL11 CAS_BL12 DATA20L13 DATA16L14 DATA18L15 NCR01 ADDR11R02 ADDR7R03 ADDR3R04 MS3_BR05 PA_BR06 BR3_BR07 RDL_BR08 CLKOUTR09 HBR_BR10 HBG_BR11 CLKDBLR12 XTALR13 SDWE_BR14 NCR15 DATA31H15 ADDR16M01 ADDR12M02 ADDR18M03 ADDR6M04 ADDR0M05 MS1_BM06 BR6_BM07 VDDEXTM08 WRL_BM09 SDA10M10 RAS_BM11 ACKM12 DATA17M13 DMAG2_BM14 DMAG1_BM15 ADSST-MEL100 Terminal Function Pin NamePin No.Pin NamePin No.Pin NamePin No.Pin NamePin No.Pin NamePin No.Pin NamePin No. TOP VIEW BOTTOM VIEW A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 B C D E F G H J K L M N P R 28 28AVR-2803/983/AVC-2870 1 45 8 2345678 1IN ABLC C1 C2 GND fo N.C.OUT Vcc Detector & Comparator Integrator TOP VIEW CXA1511M (CO: IC501) Except Japan model Head Amp Limiter Amp BPF BEF Hysteresis Comparator NJM2229S (CV: IC452) 6 79 10 13 14 15 16 811124321 5 116 Sync Sepa Sync Det Phase Det Vsync Sepa 32fH VCO 1/32 FRONT VIEW LC75721E (CO: IC101) 64 49 4833 32 17 161 AM 1 AM 2 AM 3 AM 4 AM 5 AM 6 AM 7 AM 8 AM 9 AM 10 AM 11 AM 12 AM 13 AM 14 AM 15 AM 16 AM 17 AM 18 AM 19 AM 20 AM 21 AM 22 AM 23 AM 24 AM 25 AM 26 AM 27 AM 28 AM 29 AM 30 AM 31 AM 32 G7 G8 G9 G10 G11 AA8/G12 AA7/G13 AA6/G14 AA5/G15 AA4/G16 AA3 AA2 AA1 AM35 AM34 AM33 DI CL CE RES VDD OSCI OSCO Vss TEST VFL G1 G2 G3 G4 G5 G6 Symbol VDD Vss Power terminal +5V Power terminal GND VFLPower terminal FL drive DI CL CE Serial data transfer terminal DI: Data CL: Clock CE: Chip enable OSCI OSCO External CR connecting terminal RESSystem reset terminal AM1AM35 AA1AA3 Anode output terminal AA4/G16 AA5/G15 AA6/G14 AA7/G13 AA8/G12 Anode/Grid output terminal G1G11Grid output terminal TESTLSI test terminal Function LC75721E Terminal Function BU2090F (CO: IC103) 1Vss 2DATA 3CLOCK 4LCK 5Q0 6Q1 7Q2 8Q3 9Q4 18 17 16 15 14 13 12 11 10 VDD OE Q11 Q10 Q9 Q8 Q7 Q6 Q5 CONTROL CIRCUIT 12-bit SHIFT REGISTER 12-bit STRAGE REGISTER OUTPUT BUFFER (OPEN DRAIN) BU4051BCF (CV: IC251, 252, 504507) Channel IN/OUT X4 X6 X X7 X5 INHIBIT VEE Vss VDD X2 X1 X0 X3 A B C Common Channel IN/OUT OUT/IN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4 C 6 OUT/IN 7 5 INH VEE 2 1 0 3 A B BU4053BCF (CV: IC256) Y1 Y0 Z1 Z Z0 INH VEE Vss VDD Y X X1 X0 A B C 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 C Y X X1 X0 A B Y0 Z1 Z Z0 INH VEE Y1 BU4052BCF (CV: IC255, 509, 510) Y0 Y2 COMMON Y Y3 Y1 INH VEE Vss VDD X2 X1 COMMON X X0 X3 A B 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 B X2 X1 XOUT /IN X0 X3 A Y2 YOUT /IN Y3 Y1 INH VEE Y0 29 29AVR-2803/983/AVC-2870 MM74HC4053SJ (CV: IC451) 1 2 VEE 3 4 5 6 7 89 10 11 16 15 14 13 12 Y1 Y0 Z1 Z Z0 Enable GND Vcc Y X1 X X0 C A B X = Dont Care Truth Table Control Inputs Select EnableCBAONSwitches LLLLZ0 Y0 X0 LLLHZ0 Y0 X1 LLHLZ0 Y1 X0 LLHHZ0 Y1 X1 LHLLZ1 Y0 X0 LHLHZ1 Y0 X1 LHHLZ1 Y1 X0 LHHHZ1 Y1 X1 HXXXNone TC9459F (AD: IC383) Except Japan model L-LD2 8 L-ch7 to 91decoder R-ch latch circuit R-ch7 to 91decoder 9 16 19 3 2 4 5 6 7 10 11 12 24 22 23 21 20 18 17 15 14 13 1 NC L-OUT L-IN L-LD1 L-A-GND NC NC GND CK VSSVDD NC R-OUT R-LD1 R-LD2 R-A-GND NC CS2 NC STB DATA R-IN 50kohm/ 91STEP VR Same as L-ch L-ch latch circuit Shift register (24Bit) Level shift circuit CS1 SN74HC151APW (AD: IC513, 514) SN74LV244APW (AD: IC522) Data Inputs Outputs GND Strobe 3 2 1 0 Y W 1 2 3 4 5 6 7 8 D2 D1 D0 Y W S D5 D6 D7 A D4 B C 16 15 14 13 12 11 10 9 Vcc 5 6 7 A B C 4 Data Inputs Data Select 74VHC74MTCX (AD: IC515,803) 2Q 2Q 2PR 2CK 2D 2CL