Denon-AVR1723-avr-sm维修电路原理图.pdf

D supports TMDS logic level. 48 TXC+ HDMI output Diferential Clock Output. Diferential clock output at the TMDS clock rate; supports TMDS logic level. 49 TXGND Ground TXAVDD Ground. 50 TX0 HDMI output Diferential Output Channel 0 Complement. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 51 TX0+ HDMI output Diferential Output Channel 0 True. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 52 TXGND Ground TXAVDD Ground. 53 TX1 HDMI output Diferential Output Channel 1 Complement. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 54 TX1+ HDMI output Diferential Output Channel 1 True. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 55 TXAVDD Power 1.8 V Power Supply for TMDS Outputs. 119 Pin No. Mnemonic Type Description 13 RXC_2 HDMI input Digital Input Channel 2 Complement of Port C in the HDMI Interface. 14 RXC_2+ HDMI input Digital Input Channel 2 True of Port C in the HDMI Interface. 15 HP_CTRLD Digital output Hot Plug Detect for Port D. 16 5V_DETD Digital input 5 V Detect Pin for Port D in the HDMI Interface. 17 DGND Ground DVDD Ground. 18 DVDD Power Digital Supply Voltage (1.8 V). 19 DDCD_SDA Digital I/O HDCP Slave Serial Data Port D. DDCD_SDA is a 3.3 V input/output that is 5 V tolerant. 20 DDCD_SCL Digital input HDCP Slave Serial Clock Port D. DDCD_SCL is a 3.3 V input that is 5 V tolerant. 21 CVDD Power Receiver Comparator Supply Voltage (1.8 V). 22 CGND Ground TVDD and CVDD Ground. 23 RXD_C HDMI input Digital Input Clock Complement of Port D in the HDMI Interface. 24 RXD_C+ HDMI input Digital Input Clock True of Port D in the HDMI Interface. 25 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 26 RXD_0 HDMI input Digital Input Channel 0 Complement of Port D in the HDMI Interface. 27 RXD_0+ HDMI input Digital Input Channel 0 True of Port D in the HDMI Interface. 28 CGND Ground TVDD and CVDD Ground. 29 RXD_1 HDMI input Digital Input Channel 1 Complement of Port D in the HDMI Interface. 30 RXD_1+ HDMI input Digital Input Channel 1 True of Port D in the HDMI Interface. 31 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 32 RXD_2 HDMI input Digital Input Channel 2 Complement of Port D in the HDMI Interface. 33 RXD_2+ HDMI input Digital Input Channel 2 True of Port D in the HDMI Interface. 34 CVDD Power Receiver Comparator Supply Voltage (1.8 V). 35 CGND Ground TVDD and CVDD Ground. 36 TXPVDD Power 1.8 V Power Supply for Digital and I/O Power Supply. This pin supplies power to the digital logic and I/Os. It should be fltered and as quiet as possible. 37 TXPLVDD Power 1.8 V Power Supply. 38 TXGND Ground TXPVDD Ground. 39 TXPGND Ground TXPLVDD Ground. 40 EXT_SWING Analog input This pin sets the internal reference currents. Place an 887 resistor (1% tolerance) between this pin and ground. 41 HPD_ARC Analog input Hot Plug Detect Signal. This pin indicates to the interface whether the receiver is connected. It supports 1.8 V to 5 V CMOS logic levels. 42 ARC+ Analog input Audio Return Channel Input (5 V Tolerant). 43 TXDDC_SDA Digital I/O Serial Port Data I/O to Receiver. This pin serves as the master to the DDC bus. It supports a 5 V CMOS logic level. 44 TXDDC_SCL Digital output Serial Port Data Clock to Receiver. This pin serves as the master clock for the DDC bus. It supports a 5 V CMOS logic level. 45 TXAVDD Power 1.8 V Power Supply for TMDS Outputs. 46 TXGND Ground TXAVDD Ground. 47 TXC HDMI output Diferential Clock Output. Diferential clock output at the TMDS clock rate; supports TMDS logic level. 48 TXC+ HDMI output Diferential Clock Output. Diferential clock output at the TMDS clock rate; supports TMDS logic level. 49 TXGND Ground TXAVDD Ground. 50 TX0 HDMI output Diferential Output Channel 0 Complement. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 51 TX0+ HDMI output Diferential Output Channel 0 True. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 52 TXGND Ground TXAVDD Ground. 53 TX1 HDMI output Diferential Output Channel 1 Complement. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 54 TX1+ HDMI output Diferential Output Channel 1 True. Diferential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 55 TXAVDD Power 1.8 V Power Supply for TMDS Outputs. 120 Pin No. Mnemonic Type Description 99 PGND Ground PVDD Ground. 100 PVDD Power PLL Supply Voltage (1.8 V). 101 XTAL Miscellaneous analog Input pin for 28.63636 MHz crystal or an external 1.8 V 28.63636 MHz clock oscillator source to clock the ADV7623. 102 XTAL1 Miscellaneous analog Crystal Output Pin. This pin should be left foating if a clock oscillator is used. 103 PVDD Power PLL Supply Voltage (1.8 V). 104 PGND Ground PVDD Ground. 105 HP_CTRLA Digital output Hot Plug Detect for Port A. 106 5V_DETA Digital input 5 V Detect Pin for Port A in the HDMI Interface. 107 RTERM Miscellaneous analog This pin sets the internal termination resistance. A 500 resistor between this pin and ground should be used. 108 DDCA_SDA Digital I/O HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input/output that is 5 V tolerant. 109 DDCA_SCL Digital input HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant. 110 CVDD Power Receiver Comparator Supply Voltage (1.8 V). 111 CGND Ground TVDD and CVDD Ground. 112 RXA_C HDMI input Digital Input Clock Complement of Port A in the HDMI Interface. 113 RXA_C+ HDMI input Digital Input Clock True of Port A in the HDMI Interface. 114 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 115 RXA_0 HDMI input Digital Input Channel 0 Complement of Port A in the HDMI Interface. 116 RXA_0+ HDMI input Digital Input Channel 0 True of Port A in the HDMI Interface. 117 CGND Ground TVDD and CVDD Ground. 118 RXA_1 HDMI input Digital Input Channel 1 Complement of Port A in the HDMI Interface. 119 RXA_1+ HDMI input Digital Input Channel 1 True of Port A in the HDMI Interface. 120 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 121 RXA_2 HDMI input Digital Input Channel 2 Complement of Port A in the HDMI Interface. 122 RXA_2+ HDMI input Digital Input Channel 2 True of Port A in the HDMI Interface. 123 HP_CTRLB Digital output Hot Plug Detect for Port B. 124 5V_DETB Digital input 5 V Detect Pin for Port B in the HDMI Interface. 125 DGND Ground DVDD Ground. 126 DVDD Power Digital Supply Voltage (1.8 V). 127 DDCB_SDA Digital I/O HDCP Slave Serial Data Port B. DDCB_SDA is a 3.3 V input/output that is 5 V tolerant. 128 DDCB_SCL Digital input HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant. 129 CVDD Power Receiver Comparator Supply Voltage (1.8 V). 130 CGND Ground TVDD and CVDD Ground. 131 RXB_C HDMI input Digital Input Clock Complement of Port B in the HDMI Interface. 132 RXB_C+ HDMI input Digital Input Clock True of Port B in the HDMI Interface. 133 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 134 RXB_0 HDMI input Digital Input Channel 0 Complement of Port B in the HDMI Interface. 135 RXB_0+ HDMI input Digital Input Channel 0 True of Port B in the HDMI Interface. 136 CGND Ground TVDD and CVDD Ground. 137 RXB_1 HDMI input Digital Input Channel 1 Complement of Port B in the HDMI Interface. 138 RXB_1+ HDMI input Digital Input Channel 1 True of Port B in the HDMI Interface. 139 TVDD Power Receiver Terminator Supply Voltage (3.3 V). 140 RXB_2 HDMI input Digital Input Channel 2 Complement of Port B in the HDMI Interface. 141 RXB_2+ HDMI input Digital Input Channel 2 True of Port B in the HDMI Interface. 142 HP_CTRLC Digital output Hot Plug Detect for Port C. 143 5V_DETC Digital input 5 V Detect Pin for Port C in the HDMI Interface. 144 DDCC_SDA Digital I/O HDCP Slave Serial Data Port C. DDCC_SDA is a 3.3 V input/output that is 5 V tolerant. 121 ADV7623 Block diagram CH0 CH1 CH2 VIDEO DATA DE VS HS AUDIO DATA VIDEO DATA DE VS HS AUDIO DATA VIDEO DATA DE VS HS AUDIO DATA VIDEO DATA DE VS HS AUDIO DATA XTAL XTAL1 RXA_C RXB_C RXC_C RXD_C RXA_0 RXA_1 RXA_2 VIDEO/AUDIO CLOCK GENERATION RX PLL CEC TXC TX0 TX1 TX2 5V DETECT COMPONENT PROCESSOR SCL SDATA ALSB CS I2C CONTROLLER PWRDN RESET GLOBAL CONTROLS DDCA_SDA DDCA_SCL DDCB_SDA DDCB_SCL DDCC_SDA DDCC_SCL DDCD_SDA DDCD_SCL AP0_IN AP1_IN AP2_IN AP3_IN AP4_IN AP5_IN SCLK_IN MCLK_IN AP0_OUT AP1_OUT AP2_OUT AP3_OUT AP4_OUT AP5_OUT SCLK_OUT MCLK_OUT ARC+ RX EDID/ REPEATER CONTROLLER RX HPD CONTROLLER EP_MISO EP_MOSI EP_CS EP_SCK SPI MASTER/ SLAVE EQUALIZER RXB_0 RXB_1 RXB_2 EQUALIZER SAMPLER SAMPLER RXC_0 RXC_1 RXC_2 EQUALIZERSAMPLER RXD_0 RXD_1 RXD_2 EQUALIZER CEC CONTROLLER EDID RAM SAMPLER HDMI RECEIVER PROCESSOR TRANSMITTER PACKET BUILDER HDCP ENCRYPTION ENGINE HDMI ENCODER SERIALIZER TMDS DRIVERS INT1 INT2 INT_TX INTERRUPT CONTROLLER TXDDC_SDA TXDDC_SCL TX EDID/HDCP CONTROLLER EDID/HDCP BUFFER HPD_ARC TX HPD CONTROLLER HDCP DECRYPTION ENGINE SYNC MEASUREMENT PACKET PROCESSOR INFOFRAME PACKET MEMORY AUDIO PROCESSOR ARC RECEIVER AUDIO CAPTURE HDCP KEYS TX PLL ADV7623 5V_DETA 5V_DETB 5V_DETC 5V_DETD HP_CTRLA HP_CTRLB HP_CTRLC HP_CTRLD OSD 122 LC89058W-E (DIGITAL : IC782) Pin Functions no i t cnuF O/ I emaN .oN n iP 1 RXOUT1 O RX0-6 input S/PDIF through output pin 1 2 RX0 I5(pd) 5V withstand voltage TTL input level compatible S/PDIF input pin (connected to GND when RX1 is set) 3 RX1 I(pd) Co-axial compatible S/PDIF input pin (supported demodulation sampling frequency of up to 96kHz) 4 RX2 I5(pd) 5V withstand voltage TTL input level compatible S/PDIF input pin (connected to GND when RX1 is set) 5 RX3 I5(pd) 5V withstand voltage TTL input level compatible S/PDIF input pin 6 DGND Digital GND 7 DVDD Digital power supply (3.3V) 8 RX4 I5(pd) 5V tolerable TTL input level compatible S/PDIF input pin 9 RX5 I5(pd) 5V tolerable TTL input level compatible S/PDIF input pin 10 RX6 I5(pd) 5V tolerable TTL input level compatible S/PDIF input pin 11 DVDD Digital power supply (3.3V) 12 DGND Digital GND 13 LPF O PLL loop filter connection pin 14 AVDD Analog power supply (3.3V) 15 AGND Analog GND 16 RMCK O R system clock output pin (VCO, 512fs, XIN) 17 RBCK O/I R system bit clock I/O pin (64fs) 18 DGND Digital GND 19 DVDD Digital power supply (3.3V) 20 RLRCK O/I R system LR clock I/O pin (fs) 21 RDATA O Serial audio data output pin 22 SBCK O S system bit clock output pin (16fs, 32fs, 64fs, 128fs) 23 SLRCK O S system LR clock output pin (fs/4, fs/2, fs, 2fs) 24 SDIN I5 External serial audio data input pin MOUT 39 38 37 DI RERR SLRCK SDINDO 36 42 41 40 45 44 43 48 47 46 CL CE DGND XMODE GPIO0 DVDD GPIO2 GPIO1 RXOUT2 GPIO3 INT 35 CKST 34 AUDIO 333231 LC89058W-E DVDD 30 XIN 29 DGND 2827 DVDD 26 DVDD DGNDDGND 25 XOUT XMCK 23 24 21 RDATA SBCK DVDD RLRCK RBCK DGND AGND RMCK LPF AVDD * RX5 * RX6 DVDD * RX4 * RX3 DGND * RX1 * RX2 RXOUT1 * RX0 4365871091211 21 22 19 20 17 18 15 16 13 14 * : Pull-down resistor internal at no selection 123 LC89058W-E Block diagram LC89058W-E No.A1056-4/64 Continued from preceding page. Pin No. Name I/O Function 25 DGND Digital GND 26 DVDD Digital power supply (3.3V) 27 XMCK O Oscillation amplifier clock output pin 28 XOUT O Output pin connected to the resonator 29 XIN I External clock input pin, connected to the resonator (12.288MHz/24.576MHz) 30 DVDD Digital power supply 31 DGND Digital GND 32 MOUT I/O Emphasis information | Input fs monitor output | Chip address setting input pin 33AUDIO I/O Channel status bit 1 output | Chip address setting input pin 34 CKST I/O Clock switching transition period signal output | Master/slave setting input pin 35 INT I/O Microcontroller interrupt signal output | Pins44-48 I/O setting input pin 36 RERR O PLL lock error, data error flag output pin 37 DO O CCB microcontroller I/F, read data output pin (3-state) 38 DI I5 CCB microcontroller I/F, write data input pin 39 CE I5 CCB microcontroller I/F, chip enable input pin 40 CL I5 CCB microcontroller I/F, clock input pin 41 XMODE I5 System reset input pin 42 DGND Digital GND 43 DVDD Digital power supply (3.3V) 44 GPIO0 O/I General-purpose I/O pin | Selector input pin (output referred to RDATA pin) 45 GPIO1 O/I General-purpose I/O pin | Selector input pin (output referred to RLRCK pin) 46 GPIO2 O/I General-purpose I/O pin | Selector input pin (output referred to RBCK pin) 47 GPIO3 O/I General-purpose I/O pin | Selector input pin (output referred to RMCK pin) 48 RXOUT2 O RX0-6 input S/PDIF through output pin 2 * Input voltage: I= -0.3 to 3.6V, I5= -0.3 to 5.5V * Output voltage: O= -0.3 to 3.6V * Pins 2, 4, 5, 8, 9, 10, 24, 38, 39, 40, and 41 have an internal pull-down resistor (pd). Their level is fixed when they are unselected. * Pins 32 and 33 are input pins for chip address setting when pin 41 is held at the low level. * Pin 34 serves as the input pin for designating as the master or slave when pin 41 is held at the low level. * Pin 35 serves as the input pin for configuring the I/O of pins 44 to 47 when pin 41 is held at the low level. * The DVDD and AVDD pins must be held at the same level and turned on and off at the same timing to preclude Latch-up conditions. LC89058W-E No.A1056-5/64 6. Block Diagram Figure 6.1 LC89058W-E Block Diagram Microcontroller I/F 3533 Cbit, Pc 41 INT AUDIO Demodulation & Lock detect Data Selector 24 36 XMODE RERR SDIN PLL Clock Selector Input Selector 9 10 4 5 8 44 45 13 RX5 RX6 RX2 RX3 RX4 GPIO0 GPIO1 LPF 20 RLRCK 16 RMCK 22 SBCK 23 SLRCK 1 RXOUT1 46 47 GPIO2 GPIO3 Oscillation Amplifier 29 XIN 28 XOUT 27 XMCK 34 CKST 39 CE 40 CL 38 DI 37 DO 2 3 RX0 RX1 48 RXOUT2 21 RDATA 17 RBCK 32 MOUT Fs calculator Clock Divider 124 ADSP21487KSWZ-2B (DIGITAL : IC791) ADSP21487KSWZ-2B Terminal Function TOP VIEW (PINS DOWN) 1 44 45 89 88 132 176133 PIN 1 GND PAD (PIN 177) at BOTTOM Pin NamePin No.Pin NamePin No.Pin NamePin No.Pin NamePin No. SDDQM1VDD_EXT45DAI_P1089VDD_INT133 MS02DPI_P08 46VDD_INT90FLAG0134 SDCKE3DPI_P07 47VDD_EXT91FLAG1135 VDD_INT4VDD_INT48DAI_P2092FLAG2136 CLK_CFG15DPI_P09 49VDD_INT93NC137 ADDR06DPI_P10 50DAI_P08 94FLAG3138 BOOT_CFG07DPI_P1151DAI_P14 95NC139 VDD_EXT8DPI_P12 52DAI_P04 96NC140 ADDR19DPI_P13 53DAI_P18 97VDD_EXT141 ADDR210DPI_P14 54DAI_P17 98NC142 ADDR311DAI_P0355 DAI_P16 99VDD_INT143 ADDR412NC56DAI_P12 100TRST144 ADDR513VDD_EXT57DAI_P15 101NC145 BOOT_CFG114NC58VDD_INT102EMU146 GND15NC59DAI_P11 103DATA0147 ADDR616NC60VDD_EXT104DATA1148 ADDR717NC61VDD_INT105DATA2149 NC18 VDD_INT62BOOT_CFG2106 DATA3150 NC19NC63VDD_INT107TDO151 ADDR820NC64AMI_ACK108DATA4152 ADDR921VDD_INT65GND 109VDD_EXT153 CLK_CFG022NC66THD_M110DATA5154 VDD_INT23NC67THD_P111DATA6155 CLKIN24VDD_INT68VDD_THD112VDD_INT156 XTAL25NC69 VDD_INT113DATA7157 ADDR1026WDTRSTO70VDD_INT114TDI158 SDA1027NC71MS1115SDCLK159 VDD_EXT28VDD_EXT72VDD_INT116VDD_EXT160 VDD_INT29DAI_P07 73WDT_CLKO117DATA8161 ADDR1130DAI_P13 74WD