Denon-AVR1312-avr-sm维修电路原理图.pdf

START:|qzT7t3cIXfGvpSN6RPbAWw=|i4QKmwTsguF5/wkPVABzlM4GcWQGNoMv02uNeNz1Wog=|RtRIz5LbaS+BXuKmvA5tJg=|:END D This is not a final specification. Some parametric limits are subject to change. 2 / 18 CONFIDENTIAL R2A15218FP-76A BLOCK DIAGRAM AND PIN CONFIGURATION (TOP VIEW) AGND SWC AGND SLC AGND SBLC INLB/RECL2 INRB/RECR2 INR11/RECR5 INL10/RECL4 RECR3 INL11/RECL5 FLIN1 RECL3 CIN1 FRIN1 SLIN1 SWIN1 AVEE MUTE FLIN2 FRIN2 SLIN2 SRIN2 CIN2 SWIN2 SBLIN2 SBRIN2 AVCC TREL BASSL1 BASSL2 FLOUT CC FLC FROUT AGND FRC ADCR SBLIN1 SRIN1 SBRIN1 SBL OUT ADCL SBR OUT SLOUT SBRC SROUT SWOUT SRC COUT INL5 INL1 INR1 INL2 INR2 INL3 INR3 INL4 INR4 INR5 INL6 INR6 INL7 INR7 INL8 INR8 INLA/RECL1 INRA/RECR1 INL9 INR9 SUBR SUBL DGND INR10/RECR4 DATA CLOCK BASSR1 BASSR2 TRER N.C. AGND N.C. AGND N.C. N.C. N.C. N.C. SBRCIN SBLCIN N.C. N.C. AGND N.C. N.C. N.C. N.C. N.C. N.C. N.C. MAIN SUB REC ATT 0/-6/-12/-18dB Bass/ Treble -14+14dB (2dB step) +42-95dB, -(0.5dBstep) +42-95dB, -(0.5dBstep) +42-95dB, -(0.5dBstep) +42-95dB, -(0.5dBstep) +42-95dB, -(0.5dBstep) +42-95dB, -(0.5dBstep) Tone +420dB (0.5dBstep) Tone Bass/ Treble -14+14dB (2dB step) 0-95dB, - (0.5dBstep) +420dB (0.5dBstep) 0-95dB, - (0.5dBstep) MCU I/F AVEE AVCC Bypass Tone Tone+MIX Bypass Tone Tone+MIX CMIX SWMIX MAIN SUB MAIN SUB 81828384858687888990919293949596979899100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 5049484746454443424140393837363534333231 71 R2A15218FP Terminal Functions 8-CHANNEL ELECTRONIC VOLUME With 11-Input selector And Tone control R2A15218FPR2A15218FP PRELIMINARY Notice ; This is not a final specification. Some parametric limits are subject to change. 3 / 18 CONFIDENTIAL R2A15218FP-76A PIN DESCRIPTION PIN No. Name Function 49DATA Input pin of control data 50CLOCKInput pin of control clock Output pin of FL/FR/C/SW/SL/SR/SBL/SBR channel FRIN2, FLIN2, SRN2,SLIN2, SWIN2,CIN2, SBRIN2,SBLIN2 43,42, 41,40, 39,38, 37,36 Input pin of L/R/C/SW/SL/SR/SBL/SBR channel (Multi IN 1/2) Output pin for L/R channel REC Output Frequency characteristic setting pin of L/R channel tone control (Treble)28,34TREL, TRER 26,27, 32,33 23,21, 17,15, 11,9, 5,3 FROUT,FLOUT, COUT,SWOUT, SROUT, SLOUT, SBROUT,SBLOUT BASSL1,BASSL2 BASSR1,BASSR2 FLIN1, FRIN1, CIN1,SWIN1, SLIN1,SRIN1, SBLIN1,SBRIN1 93,94, 95,96, 97,98, 99,100 Frequency characteristic setting pin of L/R channel tone control (Bass) 24,20, 18,14, 12,8, 6,2 FRC,FLC, CC,SWC, SRC,SLC, SBRC,SBLC Connects capacitor for reducing click noise of L/R/C/SW/SL/SR/SBL/SBR channel volume INL1,INL2, INL3, INL4,INL5,INL6, INL7,INL8,INL9 Input pin of L/R channel (Input Selector) 59,61,63, 65,67,69, 71,73,79 INR1,INR2, INR3, INR4,INR5,INR6, INR7,INR8,INR9 58,60,62, 64,66,68, 70,72,78 54,55ADCL, ADCROutput pin for L/R channel ADC 90,91 4,7,10,16, 19,22,56 AGND Analog ground of internal circuit 30AVCCPositive power supply to internal circuit 48DGNDDigital ground of internal circuit 52AVEENegative power supply to internal circuit 46,47SUBL,SUBROutput pin for L/R channel SUB Output RECR3,RECL3 51MUTEOutside Mute Control PIN 75,76, 81,82, 83,84, 85,86 INRA/RECR1,INLA/RECL1, INRB/RECR2,INLB/RECL2, INR10/RECR4,INL10/RECL4, INR11/RECR5,INL11/RECL5 Input pin of L/R channel (Input Selector)/ Output pin for L/R channel REC Output N.C. 1,13,25,29,31, 35,53, 57,74,77,80, 87,88,89,92 No Connected PIN 44,45SBRCIN,SBLCINInput pin for SBL/SBR channel Volume 72 NJM2595M (INPUT : IC71) TC74VHC157FT (INPUT : IC85) NJM2595 - 1 - 5-INPUT 3-OUTPUT VIDEO SWITCH GENERAL DESCRIPTION PACKAGE OUTLINE FEATURES 5-input 3-output Operating Voltage 4.0 to 6.5V Operating current 15mAtyp. at Vcc=5V Crosstalk -65dBtyp. Internal 6dB Amplifier Internal 75 Driver Bipolar Technology Package Outline DIP16,DMP16 PIN CONFIGURATION and BLOCK DIAGRAM 13 9 7 5 3 20k 20k 20k 20k 1610 14 2 1 15 11 81264 6dB Amp 75 Driver S3 S2 S4 S1 20k 20k 20k S5 S6 S7 Vin1 Vin2 Vin3 Vin4 Vin5 SW3SW4 SW5SW1SW2V+ GND V- Vout3 Vout2 Vout1 6dB Amp 6dB Amp 75 Driver 75 Driver TC74VHC157F/FN/FT/FK 2007-10-01 2 Pin Assignment IEC Logic Symbol Truth Table Inputs ST SELECT A B Output H X X X L L L L X L L L H X H L H X L L L H X H H X: Dont care (1) (15) (2) (5) (3) 1A 2A 1B (6) (10) 3A 2B (4) (9) 1Y 3Y (7) (12) 2Y 4Y EN SELECT ST 3B (14) (13) 4A 4B G1 (11) 1MUX 1 4A VCC 16 4B 15 14 13 12 11 10 1 2 3 4 5 6 7 1Y 2A 2B 2Y GND 4Y 8 3Y 9 3A 3B (top view) 1A 1B SELECT ST A S G B A Y B A Y B A Y BY 73 CS42528 (INPUT : IC84) CS42528 Block diagram 74 CS42528 Terminal Functions 75 CS497024CVZ (INPUT : IC81) 76 CS497024CVZ Block diagram M12L16161A5TG (INPUT : IC83) 77 T5CN5 (INPUT : IC91) T5CN5 Terminal Functions PinPin NameSymbolTOLERANTNch I/O TypePullupLvCnv STBY stopFunction 1AN10/PD6PROTECT-I-M3VPu-IIProtection detection pin 2AN11/PD7HDMIOST_MISI-I-IO/LDATA input pin for HDMI OST 3AVSSAVSS-Fixed GND 4VREFHVREFH-3.3V 5AVCCAVCC-3.3V 6INT4/PG3POWER_DOWN-I-M3VPu-IIPower Down detection pin 7TB9OUT/PK2FRONT_RLY-O-O/LO/LFront SP RLY control pin 8TC7OUT/PJ5SURR_RLY-O-O/LO/L Surround SP RLY control pin/Center SP RLY control pin 9TB2IN0/PH4LIMIT-O-O/LO/LCurrent LIMIT 10 TB2IN1/PH5HP_RLY-O-O/LO/LH/P RLY control pin 11TB8OUT/PG7DAC_MUTE-O-O/LO/LDAC Mute control pin 12 TEST2TEST2-OPEN 13 DVSSDVSS-Fixed GND 14 DVCCDVCC-3.3V 15 SDA2/SO2/PG4POWER_ON-O-O/LO/LPower RELAY control pin 16 SCL2/SI2/PG5CVBS_SW3-O-O/LO/LCVBS(Video) SW3 control pin 78 PinPin NameSymbolTOLERANTNch I/O TypePullupLvCnv STBY stopFunction 17 SCK2/PG6SB_MUTE-O-O/LO/LSurround Back Mute control pin 18 TEST1TEST1-OPEN 19 INT5/PF7REMOTE_IN-I-IO/LREMOTE input pin 20 TXD0/PE0TXD0-O-M3VPu-O/LO/LUPDATE TX pin 21 RXD0/PE1RXD0-I-M3VPu-IO/LUPDATE RX pin 22 CTS0/SCLK0/PE2SUB MUTE-O-O/LO/LSub Woofer MUTE pin 23 TXD1/PE4HDMI_TX-O-O/LO/LHDMI DEBUG TX pin 24 RXD1/PE5HDMI_RX-I-IO/LHDMI DEBUG RX pin 25 CST1/SCLK1/PE6HDMIOST_MISO-O-O/LO/LDATA output pin for HDMI OST 26 SDA0/SO0/PG0INT_TX-I-+3VHPu-IO/LHDMI INT TX interrupt 27 SCL0/SI0/PG1CVBS_SW2-O-O/LO/LCVBS(Video) SW2 control pin 28 SCK0/PG2HDMIOST_CLK-O-O/LO/LClock pin for HDMI OST 29 PB3HDMI_RST-O-O/LO/LHDMI Reset control pin 30 BOOT/TB0IN0/PH0/BOOT-I-M3VPu-IO/LUpdate Boot (At Update: Low) 31 TB0IN1/PH1MAIN_VOL_MUTE-O-O/LO/LVolume Mute control pin 32 TB1IN0/PH2TUNER_RST-O-O/LO/LTUNER Reset control pin 33 TXD2/PF0IPOD_TX-O-O/LO/LIPod DOCK TX communication line 34 RXD2/PF1IPOD_RX-I-IO/LIPod DOCK RX communication line 35 CTS2/SCLK2/PF2INT_RX-I-+3VHPu-IO/LHDMI INT interrupt 36 TB1IN1/PH3INT2_RX-I-+3VHPu-IO/LHDMI INT2 intreeupt 37 PB4MAIN_VOL_DATA-O-O/LO/LVolume Data line 38 TB0OUT/PI0MAIN_VOL_CLK-O-O/LO/LVolume CLK line 39 INT6/PJ6WAKE_UP-I-M3VPu-IIWAKE UP pin 40 TB1OUT/PI1TUNER_CE-O-O/LO/LTUNER CE pin 41 PB5COMPO_SW2-O-O/LO/LCOMPO_(Video) SW2 control pin 42 TB2OUT/PI2HDMI_SDA-I/O-O/LO/LHDMI SDATA 43 PB6HDMI_SCL-O-O/LO/LHDMI SCL 44 SDA1/SO1/PF4TUNER_SDIO-I/O-O/LO/LTUNER SDIO 45 SCL1/SI1/PF5TUNER_SCLK-O-O/LO/LTUNER SCLK 46 SCK1/PF6HDMIOST_CS-O-+3VHPu-O/LO/LChip Select pin for HDMI OST 47 PB7DIR_RST-O-O/LO/LDIR Reset 48 TB3OUT/PI3DIR_CE-O-O/LO/LDIR Chip Select 49 INT1/PJ1DIR_DOUT-I-O/LO/LDIR Output Data 50 CEC/PK0COMPO_SW1-O-M3VPu-O/LO/LCOMPO_(Video) SW1 control pin 51 PK1/SCOUT/ALARM DSP_DIR_CLK-O-O/LO/LDSP_DIR_CLK 52 PI4/TB4OUTDSP_DATA-I/O-O/LO/LDSP DATA 53 PI5/TB5OUTDSP_CS-O-D3VPu-O/LO/LDSP Chip Select 54 PB0/TDO/SWVDEBUG-O-M3VPu-O/LO/LMICOM DEBUG 55 PA0/TMS/SWDIODEBUG-O-M3VPu-O/LO/LMICOM DEBUG 56 PA1/TCK/SWCLKDEBUG-I-O/LO/LMICOM DEBUG 57 TEST3TEST3-OPEN 58 PJ7/INT7DSP_DIR_DATA-O-O/LO/LDSP_DIR_DATA 59 PB1/TDIDEBUG-O-M3VPu-MICOM DEBUG 60 PB2/TRS-DEBUG-O-M3VPu-MICOM DEBUG 61 PF3/RXIN1CVBS_SW4-O-O/LO/LCVBS(Video) SW4 control pin 62 DVCCDVCC-3.3V 63 DVSSDVSS-Fixed GND 64 PA2/TRACECLKHDMI_SW-O-O/LO/LHDMI Audio Data MCLK Select SW 65 PA3/TRACEDATA0CVBS_SW1-O-O/LO/LCVBS(Video) SW1 control pin 66 PA4/TRACEDATA1DSP_RST-O-O/LO/LDSP Reset control pin 67 PA5/TRACEDATA2DSP_MODE_SEL-I-O/LO/LDSP_MODE_SEL 68 PA6/TRACEDATA3CODEC_MUTE-I/O-O/LO/LCODEC Mute Control control pin 69 PA7HDMIOST_HOLD-O-+3VHPu-O/LO/LHOLD pin for HDMI OST 70 PJ0/INT0TUNER_INT-I-IO/LTUNER INTERRUPT 71 CVCCCVCC-3.3V 72 X2XOUT-XOUT 73 CVSSCVSS-Fixed GND 74 X1XIN-XIN 75 REGVSSREGVSS-Fixed GND 76 REGVCCREGVCC-3.3V 77 XT1NC-OPEN 78 XT2NC-OPEN 79 PI6/TB4IN0STANDBY_LEDR-O-O/LO/L2COLOR LED RED 80 NMINMI-M3VPu- 81 MODEMODE-Fixed GND 82 RESETRESET-I-RESET 79 PinPin NameSymbolTOLERANTNch I/O TypePullupLvCnv STBY stopFunction 83 PI7/TB4IN1EEPROM_SCL-O-M3VPu-O/LO/LEEPROM SCL 84 PH6/TB3IN0EEPROM_SDA-I/O-M3VPu-IO/LEEPROM SDA 85 PH7/TB3IN3VFD_CLK-O-O/LO/LVFD_CLK 86 PJ2/INT2VFD_CE-O-O/LO/LVFD_CE 87 PJ3/INT3VFD_DATA-O-O/LO/LVFD_DATA 88 PJ4/TB6OUTVFD_RST-O-O/LO/LVFE_RESET 89 PE3/RXIN0STANDBY_LEDG-O-O/LO/L2COLOR LED GREEN 90 TEST4TEST4-OPEN 91 PC0/AN0KEY1-I-M3VPu-IIKEY1 input pin 92 PC1/AN1KEY2-I-M3VPu-IO/LKEY2 input pin 93 PC2/AN2KEY3-I-M3VPu-IO/LKEY3 input pin 94 PC3/AN3VOL+-I-O/LO/LVOLUME UP 95 PD0/AN4/TB5IN0VOL-I-O/LO/LVOLUME DOWN 96 PD1/AN5/TB5IN1HP_DET-I-M3VPu-O/LO/LH/P DETECT 97 PD2/AN6/TB6IN0DSP_SPC1_IRQ-I-O/LO/LDSP INTERRRUPTQ 98 PD3/AN7/TB6IN1DSP_PCP_BSY-I-O/LO/LDSP BSY 99 PD4/AN8iPod_DET-I-O/LO/LiPod_DETECT 100 PD5/AN9OPTION-I-M3VPu-MODEL OPTION ADV7623 (HDMI : IC11) ADV7623 Hardware Manual Rev. 0 March 2010 16 Confidential NDA required 2.7Pin Description DDCC_SDA 5V_DETC HP_CTRLC RXB_2+ RXB_2- TVDD RXB_1+ RXB_1- CGND RXB_0+ RXB_0- TVDD RXB_C+ RXB_C- CGND CVDD DDCB_SCL DDCB_SDA DVDD DGND 5V_DETB HP_CTRLB RXA_2+ RXA_2- TVDD RXA_1+ RXA_1- CGND RXA_0+ RXA_0- TVDD RXA_C+ RXA_C- CGND CVDD DDCA_SCL 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 DDCC_SCL1108 DDCA_SDA CVDD2107 RTERM CGND3106 5V_DETA RXC_C-4105 HP_CTRLA RXC_C+5104 PGND TVDD6103 PVDD RXC_0-7102 XTAL1 RXC_0+8101 XTAL CGND9100 PVDD RXC_1-1099PGND RXC_1+1198PWRDNB TVDD1297RESETB RXC_2-1396MCLK_OUT RXC_2+1495SCLK_OUT HP_CTRLD1594AP5_OUT 5V_DETD1693DVDD DGND1792DGND DVDD1891AP4_OUT DDCD_SDA1990AP3_OUT DDCD_SCL2089AP2_OUT CVDD2188AP1_OUT CGND2287AP0_OUT RXD_C-2386DVDDIO RXD_C+2485DGNDIO TVDD2584INT_TX RXD_0-2683INT2 RXD_0+2782INT1 CGND2881DVDD RXD_1-2980DGND RXD_1+3079SCL TVDD3178SDATA RXD_2-3277AP0_IN RXD_2+3376AP1_IN CVDD3475AP2_IN CGND3574AP3_IN TXPVDD3673DVDDIO 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 TXPLVDD TXPGND TXPLGND EXT_SWING HPD_ARC- ARC+ TXDDC_SDA TXDDC_SCL TXAVDD TXGND TXC- TXC+ TXGND TX0- TX0+ TXGND TX1- TX1+ TXAVDD TX2- TX2+ TXGND CEC DGND DVDD ALSB CSB EP_SCK EP_CS EP_MOSI EP_MISO MCLK_IN SCLK_IN AP5_IN AP4_IN DGNDIO Figure 3: ADV7623 Pin Configuration 80 ADV7623 Terminal Functions ADV7623 Hardware Manual Rev. 0 March 2010 17 Confidential NDA required Table 6. Function Descriptions Location Mnemonic Type Description 1 DDCC_SCL Digital Input HDCP slave serial clock port C. DDCC_SCL is a 3.3 V input that is 5 V tolerant. 2 CVDD Power Receiver comparator supply voltage (1.8V) 3 CGND Ground TVDD and CVDD Ground 4 RXC_C- HDMI Input Digital input clock Complement of port C in the HDMI interface. 5 RXC_C+ HDMI Input Digital input clock True of port C in the HDMI interface. 6 TVDD Power Receiver terminator supply voltage (3.3 V) 7 RXC_0- HDMI Input Digital input channel 0 Complement of port C in the HDMI interface. 8 RXC_0+ HDMI Input Digital input channel 0 True of port C in the HDMI interface. 9 CGND Ground TVDD and CVDD Ground 10 RXC_1- HDMI Input Digital input channel 1 Complement of port C in the HDMI interface. 11 RXC_1+ HDMI Input Digital input channel 1 True of port C in the HDMI interface. 12 TVDD Power Receiver terminator supply voltage (3.3 V) 13 RXC_2- HDMI Input Digital input channel 2 Complement of port C in the HDMI interface. 14 RXC_2+ HDMI Input Digital input channel 2 True of port C in the HDMI interface. 15 HP_CTRLD Digital Output Hot Plug Detect for Port D. 16 5V_DETD Digital Input 5 V detect pin for port D in the HDMI interface. 17 DGND Ground Ground for DVDD 18 DVDD Power Digital supply voltage (1.8 V) 19 DDCD_SDA Digital I/O HDCP slave serial data ports D. DDCD_SDA is a 3.3 V input/output that is 5 V tolerant. 20 DDCD_SCL Digital Input HDCP slave serial clock port D. DDCD_SCL is a 3.3 V input that is 5 V tolerant. 21 CVDD Power Receiver comparator supply voltage (1.8V) 22 CGND Ground TVDD and CVDD Ground 23 RXD_C- HDMI Input Digital input clock Complement of port D in the HDMI interface. 24 RXD_C+ HDMI Input Digital input clock True of port D in the HDMI interface. 25 TVDD Power Receiver terminator supply voltage (3.3 V) 26 RXD_0- HDMI Input Digital input channel 0 Complement of port 81 ADV7623 Hardware Manual Rev. 0 March 2010 18 Confidential NDA required Location Mnemonic Type Description D in the HDMI interface. 27 RXD_0+ HDMI Input Digital input channel 0 True of port D in the HDMI interface. 28 CGND Ground TVDD and CVDD Ground 29 RXD_1- HDMI Input Digital input channel 1 complement of port D in the HDMI interface. 30 RXD_1+ HDMI Input Digital input channel 1 true of port D in the HDMI interface. 31 TVDD Power Receiver terminator supply voltage (3.3 V) 32 RXD_2- HDMI Input Digital input channel 2 complement of port D in the HDMI interface. 33 RXD_2+ HDMI Input Digital input channel 2 true of port D in the HDMI interface. 34 CVDD Power Receiver comparator supply voltage (1.8V) 35 CGND Ground TVDD and CVDD Ground 36 TXPVDD Power 1.8 V Power Supply for Digital and I/O Power Supply. These pins supply power to the digital logic and I/Os. They should be filtered and as quiet as possible. 37 TXPLVDD Power 1.8 V Power Supply. 38 TXGND Ground TXPVDD Ground 39 TXPGND Ground TXPLVDD Ground 40 EXT_SWING Analog Input Sets Internal Reference Currents. Place 887 resistor (1% tolerance) between this pin and ground. 41 HPD_ARC- Analog Input Hot Plug Detect Signal. This indicates to the interface whether the receiver is connected. Supports 1.8 V to 5.0V CMOS logic levels. 42 ARC+ Analog Input Audio return channel input 43 TXDDC_SDA Digital I/O Serial Port Data I/O to Receiver. This pin serves as the master to the DDC bus. Supports a 5 V CMOS logic level. 44 TXDDC_SCL Digital Input Serial Port Data Clock to Receiver. This pin serves as the master clock for the DDC bus. Supports a 5 V CMOS logic level. 45 TXAVDD Power 1.8V power supply for TMDS outputs 46 TXGND Ground TXAVDD Ground 47 TXC- HDMI Output Differential Clock Output. Differential clock output at the TMDS clock rate; supports TMDS logic level. 48 TXC+ HDMI Output Differential Clock Output