Denon-AVR889-avr-sm维修电路原理图.pdf

Denon Brand Company, D Edge detection is “Ed”; Detection by both shifting is “E Serial data detection is “S” (Serial data output is also “S”). Res: State at reset. “H”= Outputs High Level at reset “L”= Outputs Low Level at reset “Z”= Becomes High impedance mode at reset STBY: State of port when STANDBY mode. “O/L” = Output port and “L” “I”= Input port Stop: State of port when Stop mode. “O/L”= Output port and “L” “I”= Input port 66 AVR-2309CI/AVR-889 Sil9135CTU (DI : IC554) Functional Block Diagram 67 AVR-2309CI/AVR-889 M3062LFGPGP (DI: IC951) M3062LFGPGP Terminal Function PinPin NameSymbolI/OTypeDet Op (Int.) Op (Ext.) ResFunction 1P94/TB4VPLD DATAOC-ZVIDEO PLD control pin 2P93/TB3DIR CEOC-ZDIR control pin(LC89057W-VF4A) 3P92/SOUT3DIR DINOC-ZDIR control pin(LC89057W-VF4A) 4P91/SIN3DIR DOUTI-Lv-EuZDIR control pin(LC89057W-VF4A) 5P90/CLK3DIR CLKOC-ZDIR control pin(LC89057W-VF4A) 6BYTEBYTE-GND(Ext. data bus bit width switching, 16bit:L) 7CNVCSCNVSS-Single-chip/Micro-processor mode switching(Normal single-chip:L, Rewrite boot program start:H input set) 8P87VERSTOC-EuZReset for VIDEO ENCODER(ADV7172) 9P86VDRSTOC-EuZReset for VIDEO DECODER(ADV7401) 10RESETSUBRESETI-Lv-EuLReset input 11XOUTX1O-Oscillator connection 12VSSVSS-GND 13XINX2I-Oscillator connection 14VCCVCC-+3.3V 15P85/NMINMII-Not used(Fixed to H) 16P84/INT2CEC_INI- E Edge detection is “Ed”; Detection by both shifting is “E Serial data detection is “S” (Serial data output is also “S”). Res: State at reset. “H”= Outputs High Level at reset “L”= Outputs Low Level at reset “Z”= Becomes High impedance mode at reset STBY: State of port when STANDBY mode. “O/L” = Output port and “L” “I”= Input port Stop: State of port when Stop mode. “O/L”= Output port and “L” “I”= Input port 70 AVR-2309CI/AVR-889 Sil9134CTU (DI : IC702) Functional Block Diagram 71 AVR-2309CI/AVR-889 R2A15215 (AV : IC612) 72 AVR-2309CI/AVR-889 W9864G2GH-6 (DI : IC203) Functional Block Diagram 73 AVR-2309CI/AVR-889 Pin Function 74 AVR-2309CI/AVR-889 IS42S32200E (DI : IC903) Functional Block Diagram VCC I/O0 VCCQ I/O1 I/O2 GNDQ I/O3 I/O4 VCCQ I/O5 I/O6 GNDQ I/O7 NC VCC DQM0 WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 DQM2 VCC NC I/O16 GNDQ I/O17 I/O18 VCCQ I/O19 I/O20 GNDQ I/O21 I/O22 VCCQ I/O23 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 GND I/O15 GNDQ I/O14 I/O13 VCCQ I/O12 I/O11 GNDQ I/O10 I/O9 VCCQ I/O8 NC GND DQM1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 GND NC I/O31 VCCQ I/O30 I/O29 GNDQ I/O28 I/O27 VCCQ I/O26 I/O25 GNDQ I/O24 GND CLK CKE CS RAS CAS WE A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA0 BA1 A10 COMMAND DECODER & CLOCK GENERATOR MODE REGISTER REFRESH CONTROLLER REFRESH COUNTER SELF REFRESH CONTROLLER ROW ADDRESS LATCH MULTIPLEXER COLUMN ADDRESS LATCH BURST COUNTER COLUMN ADDRESS BUFFER COLUMN DECODER DATA IN BUFFER DATA OUT BUFFER DQM0-3 I/O 0-31 Vcc/VccQ GND/GNDQ 10 10 10 10 32 3232 32 256 (x 32) 2048 2048 2048 ROW DECODER 2048 MEMORY CELL ARRAY BANK 0 SENSE AMP I/O GATE BANK CONTROL LOGIC ROW ADDRESS BUFFER 75 AVR-2309CI/AVR-889 Pin Function SymbolPin No.TypeFunction (In Detail) A0-A1025 to 27Input PinAddress Inputs: A0-A10 are sampled during the ACTIVE 60 to 66command (row-address A0-A10) and READ/WRITE command (A0-A7 24with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. BA0, BA122,23Input PinBank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. CAS18Input PinCAS, in conjunction with the RAS and WE, forms the device command. See the Command Truth Table for details on device commands. CKE67Input PinThe CKE input determines whether the CLK input is enabled. The next rising edge of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE is LOW, the device will be in either power-down mode, clock suspend mode, or self refresh mode.CKE is an asynchronous input. CLK68Input PinCLK is the master clock input for this device. Except for CKE, all inputs to this device are acquired in synchronization with the rising edge of this pin. C S20Input PinThe CS input determines whether command input is enabled within the device. Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device remains in the previous state when CS is HIGH. I/O0 to2, 4, 5, 7, 8, 10,11,13I/O PinI/O0 to I/O15 are I/O pins. I/O through these pins can be controlled in byte units I/O3174,76,77,79,80,82,83,85using the DQM0-DQM3 pins 45,47,48,50,51,53,54,56 31,33,34,36,37,39,40,42 DQM016,28,59,71Input PinDQMx control thel ower and upper bytes of the I/O buffers. In read mode, DQM3the output buffers are place in a High-Z state. During a WRITE cycle the input data is masked. When DQMx is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. I/O0 through I/O7 are controlled by DQM0. I/O8 throughI/O15 are controlled by DQM1. I/O16 through I/ O23 are controlled by DQM2. I/O24 through I/O31 are controlled by DQM3. R AS19Input PinRAS, in conjunction with CAS and WE, forms the device command. See the Command Truth Table item for details on device commands. WE17Input PinWE, in conjunction with RAS and CAS, forms the device command. See the Command Truth Table item for details on device commands. VCCQ3,9,35,41,49,55,25,81SupplyPinVCCQis the output buffer power supply. VCC1,15,29,43SupplyPinVCCis the device internal power supply. GNDQ6,12,32,38,46,52,78,84SupplyPinGNDQis the output buffer ground. GND44,58,72,86SupplyPinGND is the device internal ground. 76 AVR-2309CI/AVR-889 Sil9185CTU (DI : IC510) Functional Block Diagram 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 20AGND R0XC+ R0XC- AVCC18 HPD0 LSCL/ EPSEL1 LSDA/ EPSEL0 RESET# EXTSWING TxC- TxC+ AGND Tx0- Tx0+ AVCC18 Tx1- Tx1+ AGND Tx2- Tx2+ 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 41R1X0- R1X0+ AVCC33 R1X1- R1X1+ AGND R1X2- R1X2+ AVCC18 DSDA1 DSCL1 RPWR1 CEC_D CEC_A AVCC33 HPD2 AVCC18 R2XC- R2XC+ AGND 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 40AGND R1XC+ R1XC- AVCC18 HPD1 I2CSEL/ INT DGND DVCC18 RPWR0 DSCL0 DSDA0 AVCC18 R0X2+ R0X2- AGND R0X1+ R0X1- AVCC33 R0X0+ R0X0- 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 61R2X0- R2X0+ AVCC33 R2X1- R2X1+ TPWR/ AGND R2X2- R2X2+ AVCC18 DSDA2 DSCL2 RPWR2 DVCC18 DGND RSVDL HPDIN TSDA TSCL I2CADDR AGND Sil 9185 80-Pin TQFP (Top View) R0X0+/- R0X1+/- R0X2+/- R0XC+/- R1X0+/- R1X1+/- R1X2+/- R1XC+/- R2X0+/- R2X1+/- R2X2+/- R2XC+/- TX0+/- TX1+/- TX2+/- TXC+/- EPSEL1/ LSCL EPSEL0/ LSDA Port0_DDC Port1_DDC Port2_DDC TX_DDC RPWR0 RPWR1 RPWR2 I2CADDR/ TPWR HPD0 HPD1 HPD2 HPDIN CEC_A CEC_D Termination/Termination/ Equalizer Oversample DPLL CEC EqualizerEqualizer Termination/ Config Logic EDID Block EDID RAM Transmitter Configuration Block Block Transmit PLL CEC I/F Receiver Block HPD Switch 5V Switch Drivers I C Switch 2 77 AVR-2309CI/AVR-889 LC89057W-VF4A (DI : IC101) 9 LC89057W Terminal Function Function Pin No. Pin Name 1RXOUTOInput bi-phase select data output terminal 2RX0ITTL compatible digital data input terminal 3RX1ICoaxial compatible amp built-in digital data input terminal 4RX2ITTL compatible digital data input terminal 5RX3ITTL compatible digital data input terminal 6DGNDDigital GND 7DVDDDigital power 8RX4ITTL compatible digital data input terminal 9RX5/VIITTL compatible digital data/Validity flag input terminal for modulation 10RX6/UIITTL compatible digital data/User data input terminal for modulation 11DVDDDigital power for PLL 12DGNDDigital GND for PLL 13LPFOPLL loop filter connecting terminal 14AVDDAnalog power for PLL 15AGNDAnalog GND for PLL 16RMCKORMCK clock output terminal (256fs, 512fs, XIN, VCO) 17RBCKO/IRBCK clock in/output terminal (64fs) 18DGNDDigital GND 19DVDDDigital power 20RLRCKO/IRLRCK clock in/output terminal (fs) 21RDATAOSerial audio data output terminal 22SBCKOSBCK clock output terminal (32fs, 64fs, 128fs) 23SLRCKOSLRCK clock output terminal (fs/2, fs, 2fs) 24SDINISerial audio data input terminal 25DGNDDigital GND 26DVDDDigital power 27XMCKOOsc. amp output terminal I/O 36 RERR1RXOUT 35 INT2RX0 34 CKST3RX1 33 AUDIO/VO4RX2 32 EMPHA/UO5RX3 31 DGND6DGND 30 DVDD7DVDD 29 XIN8RX4 28 XOUT9RX5/VI 27 XMCK10RX6/UI 26 DVDD11DVDD 25 DGND12DGND 24SDIN37DO 23SLRCK38DI 22SBCK39CE 21RDATA40CL 20RLRCK41XMODE 19DVDD42DGND 18DGND43DVDD 17RBCK44TMCK/PIO0 16RMCK45TBCK/PIO1 15AGND46TLRCK/PIO2 14AVDD47TDATA/PIO3 13LPF48TXO/PIOEN TOP VIEW 1RXOUT 32 EMPHA/UO 33 AUDIO/VO 35 INT 40 CL 39 CE 38 DI 28 XOUT 29 XIN 27 XMCK 34 CKST 41 XMODE Input Selector 2RX0 3RX1 4RX2 5RX3 8RX4 9RX5/VI 10RX6/UI 37DO 36RERR 21RDATA 24SDIN 16RMCK 17RBCK 20RLRCK 22SBCK 23SLRCK 13LPF 44TMCK/PIO0 45TBCK/PIO1 46TLRCK/PIO2 47TDATA/PIO3 48TXO/PIOEN Clock Selector C bit, U bit PLL Demodulation & Lock Detect Microcontroller I/F Data Selector I/N Modulation or Parallel Port 78 AVR-2309CI/AVR-889 HIN202EIBNZ-T (MC:IC104) Function Pin No. Pin NameI/O * For latch-up countermeasure, perform each power supply ON/OFF in the same timing. 28XOUTOX tal osc.connecting output terminal 29XINIX tal osc.connection, external clock input terminal (24.576MHz or 12.288MHz) 30DVDDDigital power 31DGNDDigital GND 32EMPHA/UOI/OEmphasis information/U-data output/Chip address setting terminal 33AUDIO/VOI/ONon-PCM detect/V-flag output/ Chip address setting terminal 34CKSTI/OClock switch transition period output/Demodulation master or slave function switching terminal 35INTI/OInterrupt output for com (Interrupt factor selectable)/Modulation or general I/O switching terminal 36RERROPLL lock error, data error flag output 37DOOcom I/F, read out data output terminal (3-state) 38DIIcom I/F, write data input terminal 39CEIcom I/F, chip enable input terminal 40CLIcom I/F, clock input terminal 41XMODEISystem reset input terminal 42DGNDDigital GND 43DVDDDigital power 44TMCK/PIO0I/O256fs system clock input for modulation/General I/O in/output terminal 45TBCK/PIO1I/O64fs bit clock input for modulation/General I/O in/output terminal 46TLRCK/PIO2I/Ofs clock input for modulation/General I/O in/output terminal 47TDATA/PIO3I/OSerial audio data input for modulation/General I/O in/output terminal 48TXO/PIOENO/IModulation data output/ General I/O enable input terminal 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 C1+ V+ C1- C2+ C2- R2IN T2OUT VCC T1OUT R1IN R1OUT T1IN T2IN R2OUT GND V- VCC +5V 2 V+ 16 T1OUT T2OUT T1IN T2IN T1 T2 11 10 14 7 +5V 400k +5V 400k R1OUTR1IN R1 1312 5k R2OUTR2IN R2 89 5k +10V TO -10V VOLTAGE INVERTER 0.1 F 6 V- C2+ C2- + 0.1 F 4 5 +5V TO 10V VOLTAGE INVERTER C1+ C1- + 0.1 F 1 3 + 0.1 F + GND 79 AVR-2309CI/AVR-889 W19B160BBT7H (DI : IC205) Functional Block Diagram 80 AVR-2309CI/AVR-889 NJW1321FP1 (AV : IC501) Control Pin Sub VSCL (27pin) VSDA (28pin) Pin NameAUX0AUX1AUX2AUX3 Signal NameOSD V/YZ1OSDVZ1OSDY- OutputD7D6D5D4D3D2D1D0 DATA2L setup00000000 H setup11111111 FunctionSuperimposeMAIN ZONEMAIN ZONENot used Signal selectCVBS signal channel selectS signal channel select L : S L : Through channel select L : Through channel select H : CVBS H : OSD channel select H : OSD channel select 81 AVR-2309CI/AVR-889 ADV7172 (DI : IC805) BLOCK DIAGRAM 82 AVR-2309CI/AVR-889 PIN FUNCTION DESCRIPTION TC74VHC244FT (DI : IC112) 83 AVR-2309CI/AVR-889 LA73053 (AV : IC101) 84 AVR-2309CI/AVR-889 LA73062V (AV : IC305) 85 AVR-2309CI/AVR-889 BU409413CFV-E2 (AV: IC301) TC4094BF (MC: IC106,107) BU4094BCFV-E2 Terminal Function TC4094BF Terminal Function DevicePin NameSymbolFunction AV : IC301 EXP1INAMAIN ZONE VIDEO(V/S) input switching EXP2INBMAIN ZONE VIDEO(V/S) input switching EXP3INCMAIN ZONE VIDEO(V/S) input switching EXP4Z2AZONE2 VIDEO(V/S) input switching EXP5Z2BMAIN ZONE VIDEO(V/S) input switching EXP6Z2CMAIN ZONE VIDEO(V/S) input switching EXP7Z1MONIAMAIN ZONE VMONITOR output switching EXP8Z1MONIBMAIN ZONE VMONITOR output switching DevicePin NameSymbolFunction MC : IC106 EXP1T.MUTETUNER MUTE CONTROL L:MUTE EXP2PREFMUTEPREOUT FRONT MUTE CONTROL L:MUTE EXP3PRECMUTEPREOUT CENTER MUTE CONTROL L:MUTE EXP4PRESWMUTEPREOUT SUBWOOFER MUTE CONTROL L:MUTE EXP5PRESMUTEPREOUT SURROUND MUTE CONTROL L:MUTE EXP6PRESBMUTEPREOUT SURROND BACK MUTE CONTROL L:MUTE EXP7PREZ2MUTEZONE2 PREOUT MUTE CONTROL L:MUTE EXP8A/DMUTEADIN MUTE CONTROL L:MUTE MC : IC107 EXP9HPRLYHEAD PHONE RELAY CONTROL H:HEAD PHONE ON EXP10FRLFRONT A SPEAKER RELAY CONTROL H:Front A Speaker ON EXP11CRLCENTER SPEAKER RELAY CONTROL H:Center Speaker ON EXP12NC- EXP13SRLSURROUND SPEAKER RELAY CONTROL H:Surround Speaker ON EXP14SBRLSURROUND BACK SPEAKER RELAY CONTROL H:Surround Back Speaker ON EXP15FBRLFRONT B SPEAKER RELAY CONTROL H:Front B Speaker ON EXP16SIRIUS RESETSIRIUS reset control STROBE 1 2 3 4 5 6 7 89 10 11 16 15 14 13 12 DATA CLOCK Q1 Q2 Q3 Q4 VSS VDD OE Q5 Q6 Q7 Q8 QS QS 86 AVR-2309CI/AVR-889 2. FL DISPLAY FLD (HCA-19MM02T) (FR: FL101) PIN CONNECTION GRID ASSIGNMENT 87 AVR-2309CI/AVR-889 ANODE CONNECTION . 88 AVR-2309CI/AVR-889 -MEMO-